SU1229765A1 - Interface for linking comuter bus with peripheral equipment bus - Google Patents

Abstract

The invention relates to automation and computing technology and can be used in automated data acquisition and processing systems using an instrument interface and a common bus interface. The device contains a register of masks and states, a register of local messages, an interrupt register, a group of I / O registers, a decoder of interface functions, an address decoder, and an exchange synchronization unit containing an interrupt vector encoder, two elements NOT, three triggers, three elements OR, three elements And, two elements AND-NOT, five pulse formers, an element OR-NOT. The device allows to increase the speed of exchange of information. 4 il. (L IND YO SO O) SP

Description

The invention relates to automation and computing technology and can be used to interface computers that have a system-wide common bus interface (OSH) interface with a standard trunk of external devices, made in the form of an instrument interface with bit-parallel, byte- consecutive information exchange.

The interface device can be used to connect the central processor with instruments and equipment in automated research systems and in process control automation systems.

The purpose of the invention is to increase the efficiency of using the computing power of a computer and to increase the speed of the information exchange process.

FIG. 1 is a block diagram of the device; in fig. 2 - block diagram block diagram; in fig. 3 and 4 - timing charts of exchange.

The block diagram of the device contains a decoder 1 of addresses, a group of information I / O registers 2, a register of 3 masks and states, a register of 4 local messages, an interrupt register -5, a decoder 6 of interface functions, a block 7 of synchronization of exchange.

The decoder 1 selects the internal registers of the device, depending on the addresses of the OS.

A group of registers 2 is used for intermediate storage and transfer of information between the OR and the trunk (WU). Register 3 is designed to write to it interrupt masks and record information about the readiness of the slave mode. software exchange of information.

Register 4 is designed to control: the interface function of controller C. Decoder 6 implements the interface functions of the transmitter T, receiver L, controller C. Register 7 is used to control the exchange of device-related information between the OR highway and the IL highway. Block 5 is designed to extract the interrupt vector corresponding to the terminating factor.

The exchange synchronization unit consists of the node 8 of the SH transmission interface function, the node 9 of the reception synchronization fiction function 9

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five

0

five

0

five

0

five

AH, node 10 of state analysis of interface functions and node 11 of generating interrupt signals.

When this node interface functions SH contains the element NOT 12, the delay element 13, the element And 14, the element AND-NOT 15 and 16, the trigger 17, the driver 18 pulses. The node of the AN interface function contains the element NOT 19, the elements AND 20 and 21, the elements OR NOT 22 and 23, the trigger 24, the drivers 25 and 26

-1PULSES.

The interrupt signal generating node contains the elements OR 27 and 28, the trigger 29, the pulse shapers 30 and 31. The node of state analysis of interface functions is implemented as an interrupt vector encoder.

The interface operates as follows.

The computer communicates with the device with the help of internal registers, and the connection between the device and the main line of the control unit is carried out without the participation of the computer. Internal registers 2-4 are accessible by computers and the latter can access them in write and read modes in accordance with the OSH interface algorithm.

The procedure of information exchange is concluded in the following. In the mode of receiving information in a computer (Fig. 3), register 2 generates a read receive readiness signal indicating the readiness of the I / O register to record information in it, then register 7 generates readiness signals of the device to receive a byte information. A VU connected to the trunk puts data bytes of information onto the data bus and gates its data with a signal. Block 7 receives this signal and the AN interface function enters the ACDS state. Register 5 analyzes the possibility of receiving a byte and by gate output exposes the permission to issue an interrupt vector for block 7. The latter sets an interrupt requirement (TPD) for the ORR, npKttmiaeT interrupt provision (PNR) and generates a sync pulse (sip) signal according to the work protocol FROM, in addition, block 7 generates a-signal C and B for block 5. Signals C and B are sensed by block 5 and the latter sets the interrupt vector to the SNR corresponding to the mode of receiving information. Having received the interrupt vector, the EY4 goes to the receive-information program. Block 7 generates a second CMU signal, over which the computer records a byte of information.

When the next byte is received, the procedure is repeated. In the mode of transmitting information from the computer to the backbone WU, the node 8 of the block 7 enters the transmission state and the interface function SH of the block 7 enters the SGNS state. Register 5 analyzes the possibility of an interrupt for transmitting information (similar to the mode of receiving information) If the interrupt is enabled, the procedure for issuing an interrupt vector to the OR and the operation of the synchronization signals is similar to that described. Upon receipt of the interrupt vector, the computer proceeds to the data byte transfer program. By the second signal, the CIP byte is written to register 2, after which the last generates a byte signal indicating that information can be read from register 2. Next, the transfer of bytes occurs asynchronously when the device-receiver connected to the mainline is ready.

The proposed interface can function in the exchange mode of device-dependence of information practically asynchronously with respect to the operation of a computer. This allows the main computer time to be used for pem.g- tasks that are not related to the process of exchanging information with the backbone and thus making the most of the computing resources of the computer, exchanging information in real time with various groups of interface devices. .

Claims (1)

Invention Formula A device for interfacing a computer trunk with a trunk of external devices (WU) containing a register of maso and states, a register of local messages, a register of interruptions, a group of input-output registers, a decoder of interface functions, and a decoder of addresses, and the information outputs of the register of masks and states, the register of local messages, the interrupt register, the group I / O registers are connected to a bi-directional information bus of a computer mainline, the inputs of the address decoder are connected to the output information bus of a mainline COMPUTER, and i vsodna bus magist, y j 2o 25 , 0 computer relay Input of information is connected to the first gate of the register of masks and states, the gate of the register of local messages, the first gate of the input I / O registers of the group and the first gate of the address decoder, the output bus of the mainline of the computer. The information is connected to the second gate of the register of masks. and states, the second gating inputs of the group I / O registers and the second gating input of the address decoder, the third gating input of which is connected to the output bus synchronization of the mainline of the computer, and the first output of the address decoder is connected to the enabling input of the register of masks and states, the information output of which is connected to the information input of the interrupt register, the information output of the register of local messages is connected to the input of the decoder of the interface functions, the first output of which is connected to the bus bus devices, the inputs of the selection of the I / O registers of the group are connected to the sec | 5gm output of the address decoder, the third and fourth outputs of which are connected by but with the synchronization bus of the computer trunk and with the enabling input of the local message register, characterized in that, in order to increase the speed of the exchange, an exchange synchronization block is inserted in the device containing the interrupt vector encoder, two elements NOT, three elements OR, three triggers, - three elements AND two elements NAND, five pulse shapers and an element OR NONE, the second and third outputs of the decoder of the interface functions are connected respectively to the first inputs of the first AND element and the first element AND, and the outputs The presence of byte and readiness of receiving the byte of group I / O registers are connected respectively to the inputs of the first and second elements NOT, the first, second and third inputs of the second element AND are connected respectively to the second output of the decoder of the interface functions, the output of the first element NOT and the output of the delay element, input which is connected to the bus line VU Readiness reception and the output of the first pulse shaper, the input of which is connected to the output of the first element And, the first and second inputs of which are connected respectively but with the first and second inputs of the third element AND, the output of the second element is NOT connected to the third input of the first element AND, the first input of the OR-NOT element and the zero input of the first trigger, the single input of which is connected to the output of the first OR element, the first input of which is connected to the output the second pulse generator, the second input of the OR-NOT element and the bus bus BU Data gating, the second input of the first element OR is connected to the combined outputs of the discharge until Ready to receive a byte of the input / output registers of the group the terminal is connected to the third input of the third element AND, the output of which through the third pulse shaper is connected to the first input of the second NAND element and the WU main bus data is received, the single and zero inputs of the second trigger are connected respectively to the outputs of the second AND and NAND element, The presence of a byte and the second input of the first NAND element, the third input of which is connected to the output of the second trigger and the input of the second pulse former, the first The second and third inputs of the interrupt vector encoder are connected to the service request bus, respectively, to the service request, the outputs of the first NAND element and the first trigger, the first and second outputs of the interrupt vector encoder, are connected to the interrupt register enable input and to the mask register and state identification output The bit output of the bit. Confirmation of the service of the interrupt register is connected to the single input of the third trigger and to the first input of the second OR element of the synchronization block The second is connected to the gate input of the interrupt register, the output bus lines of the computer input and the representation of the interrupt are connected respectively to the first input of the third element OR and the zero input of the third trigger of the synchronization block of the exchange OR connected to the second inputs of the second and third elements OR through the fourth pulse shaper connected to the input synchronization bus of the mainline of the computer, and the output of the third trigger through the fifth pulse shaper connected to the input bus m gistrali computer prershani requirement. IITT Fig.i Yu l "g ll HXfl / us Mfs X rnf  at nftf  / ctra X / H / mt $ z. 9sh.3 M x l " D4G ( nrp X / y  x Compiled by G, Sternin Editor M, Blanar Tehred G. Gerber Proofreader S. Cerny Order 2451/49 Circulation 671 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 y / z / Subscription