SU1300485A1 - Interface for linking electronic computer with peripheral equipment - Google Patents

Abstract

The invention relates to automation and computing technology and can be used in hierarchical decentralized automated process control systems in various industries. The aim of the invention is to improve the noise immunity of the device. The device contains amplification blocks 1 and 2, control block 3, interrupt block 6, exchange block 5, first receiving register 7, New is that galvanic separation elements 10 are entered, second control block 9 and second receiving register 8, the Device provides the communication of the electronics-60 microcomputer with local controllers, logic control devices, technologists' consoles and means of collecting information in conditions of a high level of longitudinal impulse noise caused by inductive coils of chemical reagents Ktorov 1 ZP f-ly, 8 silt, SO computer with nepu pepia 4 00 ate

Description

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11300485

The invention relates to automation and can be used in hierarchical decentralized process control systems, in which at the lower level of automation communication is connected to a computer (usually a microcomputer) with local automation equipment (control and management consoles, controllers, programmable logic controllers, acquisition devices and primary processing of information such as loggers, etc.) is carried out at distances of several tens (less often hundreds) of meters and under conditions of intense industrial interference and at a data exchange rate of about 2000 3000 words per second.

"The purpose of the invention is to improve the noise immunity of the device.

FIG. 1 is a block diagram of the device; in fig. 2-7 are functional diagrams of the first control unit, the exchange unit, the mode register, the interrupt unit, the first and second receiving registers (with galvanic separation), and the second control unit, respectively.

FIG. 8 is a time chart of the operation of the device (as applied to a variant of a specific implementation).

The device contains units 1 and 2 of amplification of computer interfaces and peripheral devices, the first control unit 3, which is essential for organizing the operation of the device by the signal of the first interface, a register of 4 modes defining the algorithm of operation of the device 20

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the first interface, the exchange unit 5, organizing the transfer of information between the first and second receiving registers in accordance with the contents of the register of 4 modes, block 6 preorganizations, organizing the interruption of the computer program by signals of the second control unit, the first 7 and second 8 receiving registers, forming ring register for transferring data from one interface to another, the second control unit 9, which organizes the interaction of the second receiving register 8 with the exchange unit 5 and the second interface, elements 10 galvanic p the divisions (optocouplers) intended for the galvanic separation of the signals of the first and second interfaces.

The control unit 3 (Fig. 2) contains the elements 11, 12 of the comparison, the element NO 13 and the trigger 14.

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The exchange unit 5 (FIG. 3) contains a generator of 15 clock pulses, an element NOT 16, the first element AND-OR 17, a trigger 18, an element NOT 19, an element EPI 20, a driver (waiting for a single vibrator) 21, a second element AND -OR 22.

The mode register 4 (FIG. 4) of the device is AND 23, a register 24 for storing the two-bit code, and the OR element 25.

Interrupt block 6 (Fig. 5) contains an OR-NOT 26 element, interrupt signal register 27 driver

5 28 impulses for damping mechanical bounce of contacts, element NO 29.

An annular register with elements of galvanic separation (Fig. 6) combines elements 30-32 of the first receiving register 7, elements 33-35 of galvanic separation on optrons, and a second receiving register 8 on elements 36-38.

The control block 9 (Fig. 7) contains the element NOT 39, the element OR 40, the element AND 41, the group of elements AND 42, the pulse shaper 43, the pulse shaper (the waiting vibrator) .44.

The first interface is a unified trunk system of a central computer between the processor, the operative memory

2 and peripheral devices. Communication between devices participating in the exchange is carried out in an asynchronous manner.

The second interface is a coherent unified system of trunk links for data and control signals and radial links for peripheral sampling signals. Connection between central

5 and. the peripheral parts of the interface is controlled by the central part.

The device works as follows.

Each device connected to the second interface corresponds to an address in the computer memory. The device exchanges data between computers using the first interface

5 and devices connected to the second interface in the program exchange mode, as well as the organization of the interrupt mode by the signal of the second interface.

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In the program exchange mode, the device operates as follows.

Two typical operating cycles of the device are performed, one of which involves contacting the peripheral device at the specified address in order to receive information from it, and the second - accessing the peripheral device to send it the necessary information. Thus, in each cycle, a two-stroke operation of the device is provided.

In the first cycle of the computer, via the amplifier of the unit 1, sends the command to start operation to block 3 (trigger 14), two-digit mode code to the register 4 and hexadecimal code of the peripheral device to the inputs of the receiving register 7 (data). In accordance with the output signals of the register 14 and element & 23 block

5 organizes the translation of data from receiving trigger 7 through element 10 to receiving register 8, in which case a parallel-to-parallel conversion of data occurs.

At the end of the broadcast, the receiving register 8 notifies the block 9, which organizes data to the second interface through the amplifiers of block 2 with the corresponding accompanying signals from AND 42 elements and notifies via the OR 40 block 5

06At the end of the first cycle cycle (40 After addressing, the selected peripheral device exposes a 16-bit data code to the buses of the second interface, fed through the amplifiers of block 2 to the receive register

8, while block 9, through element I 41, notifies by switching on trigger 18, block 5, which starts translating data from receiving register 8 through elements 10 to receiving register 7. At the end of the broadcast, block 5 notifies block 3, according to a signal from which register 27 set At the computer input there is a request for service signal, which is removed after the computer is read through the data amplifiers of block 1 from the outputs of the receive register 7. This completes the cycle.

The operation of the device in the first cycle of the second cycle is similar to the first cycle of the second cycle, but another code is supplied to register 4, and at the end

The first cycle, block 9, through block 5 and block 3, in register 27, at the input of the computer, sets the signal for the end of the first cycle.

  In the first cycle of the computer, via block 1, it issues a start command to control unit 3 (element 14), a two-bit mode code at the input of the mode register 4 (24) and a sixteen-bit code of the address of the peripheral device to the inputs of the receiving data register 7.

In the second cycle of the second cycle, the computers, through the amplifiers of unit 1, expose

5 to the inputs of the receiving register 7, a hexadecimal information code intended for transmission to the addressed device. Further work takes place, as in the first measure,

0 which ends with a computer notifying signal of the end of the second cycle, produced by the block 6. This signal is reset upon a computer command.

5 The computer interrupts the device using register 27 of block 6 upon receiving a corresponding request from the second interface, which passes through block 2 and element 10, while the computer stops the program exchange and starts processing the interrupt. The signal is reset by a computer command through an OR-NOT 26 element.

The time diagram (Fig. 8) shows two modes (cycles) of the device operation: 1 mode - receiving information from a peripheral device (PU) into a computer at the request of a computer; 2 mode0 transfer information from the computer to the addressed PU.

Each mode includes an identical cycle of addressing the PU. On the falling edge of the command, the data is output from the computer under control of block 3, the PU address is written through block 1 to register 7, and the generator 15 starts on block 5, after the addresses from register 7 are changed through element 10 to register 8, generator 15 stops and block 9 generates on the element And 42 team VdA, during which the address through block 2 enters the bus interface peripherals.

5 In the 1st mode after testing the PU (after a time of no more than 1 ms), the I / O signal is generated, arriving at the input of the generator 44 of block 9, in which the delay 5

ka and the formation of a working pulse for recording and switching on the generator 15, coming through element 10 into block 5. After overwriting the data of register 8 into register 7, generator 15 stops and block 6 generates a signal. Requirement A to the first interface via block 1. The signal is reset by the rear front. Signal Data input after reading data by the first interface.

The 2nd mode consists of two clocks similar to the tact of addressing PU. The difference is that in the first cycle, block 9 generates an I / O signal instead of VdA, and in both cycles after reading addresses and data by the second interface, block 9 generates a signal through blocks 10, 5, 3 and 6. Requirement A. Reset of the signal Tre ; - A is raised by the leading edge of the data output signal) at the beginning of the 2 clock cycle, or by the A / B / first interface reset signal.

The third mode of operation of the device is the service mode of the interrupt, which is implemented as follows.

The second interface with the signal Avari through block 2 and elements 10 initiates in block 6 the signal Requirement B, which enters the first interface. The reset is performed by the falling edge of the signal. Reset B.

The control unit 3 (Fig. 2) operates as follows.

Signal The data output from the amplifiers of the first interface of block 1 is gated with the signal from block 5 and sets trigger 14 through elements 13 and 12. The output signal from the trigger enters block 5 to start the generator 15.

The trigger 14 is reset to its initial state after the gating through element 11 finishes rewriting the signal from block 5. The same gated signal from the output of element 11 enters. block 6 to turn on mode 2 signal Requirement A.

The exchange unit 5 (FIG. 3) works as follows.

The GTI Trigger signal from block 3 turns on the generator 15, and the trigger 18, depending on the presence of a stop signal, sets the GTI element on the AND-OR 17 element to the initial phase of operation of the generator 15. As a result, the output registers 7 and 8 receive a sync - ma with a certain phase. The phase change of the generator 15 to the opposite is carried out when signals are applied Data input or GTI control.

The HE element 19 and the OR element 20 are designed to generate the reset signals in the device, and the shaper 21 and the AND-OR element 22 are used to synchronize the operation of the device.

The mode register (figure 4) works as follows.

Signals are input to elements 23, 24, and in the presence of a signal, the Record is memorized.

At the same time, in the second cycle of mode 2, the PR reset signal through the OR 25 element is input to block 6, the mode entry signal is sent to the first receiving register 7, and the work organization signal is sent to the exchange unit 5. The Reset signal sets the register 24 to the initial state.

Interrupt unit 6 (FIG. 5) operates as follows.

Signals Reset or Reset B from blocks 3 and 1 through the element OR-HE 26 block 6 is brought to its original state. Signals T.A. signals from block 3 arriving at register 27. An interrupt signal is generated. Requirement A, actions received at block 1.

The Avariya signal, which comes from block 2 through element 10, element NOT 29 and driver 28, generates an interrupt signal in register 27. Requirement B for block 1.

The control unit 9 (Fig. 7) operates as follows.

By means of the Stop signal received from register 8, e.pement NO 39 prohibits the passage of a signal from the second interface and opens element I 42 to form strobe signals. VdA and. In this case, via the OR 40 element, the Control signal is formed. The GTI to block 5. The I / O signal from block 2 starts the driver 44, which triggers the working impulse to start the generator 15, which arrives at the resolution on the AND 41 element in block 3.

Receiving registers 7, 8 and electroplating elements 10 (Fig. 6) operate as follows.

Signal The recording of the mode is fed to the input of element 30 at the second cycle of cycle 2. Each of the receiving registers operates with a 16-bit data code. The sync signal is fed to the synchronous inputs of elements 30-32 and through the optocoupler 33 to the synchronous inputs of elements 36-38. The Stop signal comes from the output of element 36 to block 9 at the end of the transmitted information.

Overwriting the first interface-second interface occurs from the output of the seventh bit of element 32 through

peripheral interface amplification, characterized in that, in order to improve the noise immunity of the device, a second control unit, a second reception register and a group of galvanic separation elements are entered into it, and the input and output of the tracking signals of the second control unit are connected respectively to the first output and input of the unit interface gain of peripheral devices, the second input and output of which are connected respectively to the input and output of the paralleleptron 35 to the input of the element 36, the second 5th code of the second when multi-register-interface-first interface from the output of the seventh bit of the element 38 through the optocoupler 34 to the input of the element 30. In all figures, the symbol 1 is signed, and the third output through the corresponding element of the galvanic separation of the group - with the input Avari of the interrupt unit, input and the output of the sequential code of the first receiving register is connected through the corresponding elements of the galvanic separation of the group with the output and the input of the serial code of the second receiving register, the output of the discharge of which is connected to the synchronizing the second control unit moves, and which output start sinkrovhod second receiver register elements are connected via respective galvanic separation to the control input and the output clock exchange unit,

It assumes that a constant level of logical 1 is applied to this input of the element.

Claims (2)

1. A device for interfacing a computer with peripheral devices, comprising a first control unit, an exchange unit, a mode register, an interrupt unit, a first reception register and a computer interface gain unit, the first and third inputs of which are connected respectively to the output of the interrupt unit, the output of the signals of the exchange unit mode and the output of the parallel code of the first receiving register, the input / mode of which is connected to the first output of the mode register, and the sync input to the output of the synchronization pulses of the exchange unit whose start input is connected to the first at the output of the first control unit, the second output and the first input of the interrupt block connected respectively to the input and the first output of the computer interface gain block, the second to fifth outputs of which are connected respectively to the first reset input of the interrupt block, the input of the parallel code of the first receiving register n information input mode register, the second and third outputs of which are connected respectively to the second input of the interrupt unit, the input of the ima exchange unit, which reset output is connected to the second input of the first control unit, and block peripheral interface amplification, characterized in that, in order to improve the noise immunity of the device, a second control unit, a second reception register and a group of galvanic separation elements are entered into it, and the input and output of the tracking signals of the second control unit are connected respectively to the first output and input of the unit interface peripheral devices, the second input and output of which are connected respectively to the input and output of the parallel code of the second receiving register code of the second receiving register Pa, and the third output. Through the corresponding element of the galvanic separation of the group - with the input of the Avari Interrupt block, the input and output of the serial code of the first receiving register are connected via the corresponding elements of the galvanic separation of the group with the output and input of the serial code of the second receiving register, the output of the readiness digit of which is connected from the synchronization inputs of the second control unit, the start output of which and the sync-input of the second receiving register are connected via the corresponding elements gal separation with a control input and output of an exchange unit clock, 2. The device according to claim 1, wherein the second control unit comprises an AND element, an OR element, an NOT element, two pulse generators and a group of H elements, the output of the OR element is the block start output, the first input connected to the output of the element And, the first input of which is connected through the element NOT to the first input of the first element AND of the group, the first and second the inputs of the second element AND group and the synchronizing input of the block, the output of the element is NOT connected to the first input of the third element AND group, the output of the second element AND group is connected to the second input of the OR element and through the first pulse shaper - to the second inputs of the first and third elements AND group, the outputs of which form the output of the data tracking signals of the block, the second input of the And element is connected through the second pulse shaper to the input of the tracking signals of the data block. RSOO 0 / n $ l. one PC01 GSH Record Overload mode S reg. 2 To receive register7 D with D I l 25 CSpOC PR K blocks 6 organic raeot KSflongS Fy From inS f / gd TreyA J 26 OmSfl.1 C (grew P requirement A ipeooiuHueB } Kfff .; Kt 2B 9m regs: ....... flvw4 / Qmfy.l Kfmgl l ujr - KdflOKyy Dunnsh KSfl.l c / gg uz.6 Sm reception. to femcnj.S Otn6ma2 8) fo9 9TH Record pi 89A B $ / 8tttu TpeSoluHutH 8M saunas Marie TpfSolaHueS ResetS Editor N. Shvydka Compiled by V. Vertlib Tehred A. Kravchuk Proofreader. Cherni Order 1150/48 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 KSh U2.7