SU1315988A1 - Interface for linking electronic computer with peripheral device - Google Patents

Abstract

The invention relates to computing and is intended for interfacing computers with software-controlled external devices. The aim of the invention is to expand the functionality by providing the possibility of using separate bus addresses and data for connecting to a computer Electronics-100 / 1b and an external device controlled by a computer Electronics-60. The device contains a block of channel transmitters, a block of channel receivers, blocks of 5, 6 channel transceivers, output buffer register 7, interrupt vector address register 11, data multiplexer 4, state register 9, decoder 2 addresses, decoder 3 control signals, block 10 interrupts. 13 ill., 2 tab. (L 13 co. 00 00 Yl.G

Description

1. 13

The invention relates to computing and is intended for interfacing computers with software-controlled external devices.

The aim of the invention is to expand the functionality by providing the possibility of using separate address and data buses for connecting to the Electronics-100/16 computer and an external device controlled by the Electronics-60 computer.

FIG. 1 is a block diagram of the device in FIG. 2 is a block diagram of channel receivers in FIG. 3; a diagram of an address decoder; FIG. 4; a diagram of a control signal decoder; FIG. 5 is a diagram of a data multiplexer and an interrupt vector address register; in fig. 6 is a diagram of the first channel transceiver unit; FIG. 7 is a diagram of the second channel transceiver unit; in fig. 8 is a diagram of the output buffer register; in fig. 9 is a block diagram of channel transmitters; FIG. 10 is a state register diagram of FIGS. 11 and 12 is a priority block diagram; in fig. tS - register formats.

The device (Fig. 1) contains a block

1 channel receivers, descrambler

2 addresses, a decoder 3 control signals, a data multiplexer A, the first 5 and second 6 blocks of channel transceivers, an output buffer register 7, a block of 8 channel transmitters, a state register 9, an interrupt block 10, a register 11 address of the interrupt vector j, a data bus 12, bus 13 addresses, inputs and outputs 14-31 devices.

Block 1 channel receivers (Fig. 2) contains channel receivers 32-47.

The address decoder 2 (FIG. 3) contains the elements HE 48-57, the elements AND-NOT 58.59, the element NOT-AND 60, the element AND-NOT 61, the element NOT 62, as well as the switches K1, K2, short-circuit. Using these switches, the device address is set (task address 767770).

The decoder 3 control signals (Fig. 4) contains the element NOT 63, the element AND-NOT 64, the element NOT 65, the element AND-NOT 6, the elements NOT 67-72, the element NOT-AND 73, 74, the elements AND-NOT 75-82, HE elements 83-87, resistance elements 88-91, capacitor 92.

9882

Data multiplexer 4 (FIG. 5) j contains AND-HE elements 93, 94, multiplexers 95-98. The address register of the interrupt vector forms the contacts, the K4 switch (assigned addresses for the interrupt vector A-300 and B-304).

The channel transceiver unit 5 (FIG. 6) contains channel transceivers 99 and 100. The channel transceiver unit 6 (FIG. 7) contains a NOT-OR element 101, a HE element 102, channel transceivers 103 and 104.

The output buffer register 7 5 (Fig. 8) contains the registers 105-108.

Block 8 channel transmitters (Fig. 9) contains channel transmitters 109-111.

The state register 9 (FIG. 10) is composed of a register 112.

Interrupt unit 10 consists of two parts.

The first part (Fig. 11) contains the elements AND-NOT 113-121, the elements 5 NOT-AND 122-126, the elements SH-NOT 127-131, the elements NOT-OR 132-139, the element AND 140, the element NOT-OR- HE 141, triggers 142-144, resistances 145-147, capacitor 148. 0

The second part (Fig. 12) contains the elements AND-NO 149-156, the elements NOT-AND 157-161, the elements OR-NOT 162-165, the elements NOT-OR 166-169, the element 5 And 170, the element NE-NILI-NOT 171 , triggers 172-174, resistances 175-177, capacitor 178, HE element 179.

Channel receiver unit 1 (Fig. 2) is intended to receive from device 0 a computer channel via bus 13 a device address (KADRON-17H), via bus 14 a synchronization signal of the active device (KSAN), bus 15 and 16 of operation control signals in a CB / VON 5 and KV / V1N.

The presence of the letter K in front of the signal name indicates that the signal belongs to the computer channel. The presence of the letter B or H after the signal name 0 indicates a high or low level of this signal.

The decoder 2 works as follows.

A computer (not shown in Fig. 1), referring to an external device through a interface device, sets up an address (13 KADRON, FR 17N) and a XAN signal on bus 13 and on bus 14. Through block 1, these signals enter the decoder,

2, with the SALADR 17B, ADR16, ADR15B, ADR14, ADR13B signals at the inputs of the AND-NE 61 element.

If the address received by decoder 2 via ADROSV, ADR12V lines with the address set by switches K1, K2, short, matches, the inputs of the AND-NOT elements 58 and 59 receive high-level signals, and on their outputs in this case there are signals low level, which arrive at the inputs of the element NON-60. At the output of the element: NOT-AND 60, a high signal is generated; the level arrives at the input of the element AND-KE 61. Thus, all inputs of the element AND-NE 61 contain signals a high level and the output of the HE element 62 is set to a high level signal OYSTVO selected, which allows the operation of the decoder 3.

The decoder 3 determines the operating mode of the entire device in accordance with. three minor address bits

ADROOV, ADR01V, ADP02S and. control- 25 encoder 3 or VEKN from the block by 10 signals В / В1В and В / ВОВ. These signals are sent to the decoder 3 control signals, which at the same time absorb the corresponding signals that control the internal valves of the device, the output signals of DATA INPUT and DATA OUTPUT for an external device, as well as with some delay the signal of the TSCN, the incoming transponders 103, 104 receive the information of the OEP, D07B from the multiplexer 4 and place it on the computer data bus 12 (Fig. 7). 30 Vpsodny buffer register 7

(Fig. 8) consists of two 8-bit registers, which allow the output of 16-bit words or 8-bit bytes from a computer channel during

tire 17 in the computer. The output is specified- 35 external device (Fig. 1). The first

The 8-bit register consists of two registers 105 and 106, each of which consists of four D-triggers, a ger with common reset inputs, and a frame;

These signals occur only when there is a high-level signal. DEVICE SELECTED, arriving at the decoder 3 from the decoder 2 addresses.

A device is represented by a computer as three address registers: a register with a stop, an output register and an input register.

The control signals of the decoder 3, which are determined by the address bits of ADROOV, ADR01B, ADR02V, and signals B / B1 B and B / BOB, are given in Table. one.

The data multiplexer selects information from four sources (group 50 of which are VDOOV-VD07V signals of inputs 24, output buffer register 7, status register 9 and address of interrupt vector) and places it through block 6 on bus 12 of computer data (Fig. 1) . Through the multiplexer, only the content of the low byte is transmitted to the computer channel (bus 12), the content of the high byte goes directly through block 5 or block 8.

The multiplexer is controlled by the signals ADR01N, ADR02N and VEKN.

In tab. 2 shows the dependence of the choice of the source of information on the control signals.

Block 5 receives the bus 12 (Fig. 1) data from the computer (KD08N, KD15N) and transmits to the output buffer re-.

O gistr 7. When a control signal is received from the decoder 3, INPUT AN, the channel transceivers 99-110 receive information (BB08B, BB15V) from the external device via bus 24

5 and exposes it onto the computer data bus 12 (Fig. 6).

Unit 6 receives the bus 12 (Fig. 1) data from the computer (KDUN KD07N) and transmits them to the inputs of the register 7

0 (DOOV, D07V) and to the inputs of register 9 (pre, D01V, D05V, .D06V). When a non-OR 101 element arrives at any of the control signals (HE INPUT, INP 2H, INP 4H) from the transceivers 103, 104, they receive the information from the DOOV, D07B from the multiplexer 4 and put it on the computer data bus 12 (Fig. 7). Vpsodny buffer register 7

(Fig. 8) consists of two 8-bit registers, which allow the output of 16-bit words or 8-bit bytes from a computer channel during

external device (Fig. 1). The first

The 8-bit register consists of two registers 105 and 106, each of which consists of four D-flip-flops with common reset and construction inputs;

quantization (Fig. 8). The second 8-bit register consists of similar registers 107 and 108. The two control signals OUTPUT 2 and OUTPUT 2 MBV and OUTPUT 2 UAC, produced by decoder 3, are gating for 8-bit registers (Fig. 8). The control signal OUTPUT 2 MBV gates the writing of the DOVV-D07V data from block 6 to registers 105, 106, from the outputs

sink to the output bus 22 and to the multiplexer 4. The control signal OUTPUT 2 SBB gates the data record D08V-D15V from block 5 to registers 107, 108, 55 from the outputs of which the signals VD08V, VD15V go to the output bus 23 and block 8 of channel transmitters . In block 8 channel transmitters to the inputs of transmitters 109 and 110 post51

VD08V signals are received from the register 7. When the strobe signal enters 2H from the decoder 3, the information from the inputs is transmitted to the computer data bus 12, At one of the inputs of the transmitter 111, a WB REQUIREMENT signal is received from the external device via the bus 30. When the gating signal is entered ENTER OV from the decoder 3 information from the input of the transmitter 111 enters the line KD 15N bus 12 data.

The state register 9 (FIG. 10) has six bits. Four of them can be loaded and read programmatically and executed on register 112, which contains four D flip-flops with common reset and gate inputs: RSOO bits, RSOOV bits that can be used to simulate interrupt requests in the offline test mode, and bits PC05 and PCBs that control the interrupt logic of the device. Signals DOOV, D01B, D05B, ADBB from block 6 are sent to the inputs of the register 112. When a strobe signal is received from the decoder 3, the OVB output information from the inputs is written to the D-flip-flops, RSOOV, PCOBB signals from the D-trigger signals Register 112 is sent to multiplexer 4 and computers can be read through it,

In addition, the signals PCOOV and PC01B are received respectively at the outputs 25 and 26 of the device, and the signals PC05B and PC06B (signals RESOLUTION BV and RESOLUTION AB, respectively) go to interrupt unit 10 (FIG. 1)

As another two bits PC07 and PC15 of register 9, we can consider the signals REQUIREMENT AB and REQUIREMENT BV, respectively (in FIG. 10 not shown), which can only be read by software. Signals REQUIREMENT AB and REQUIREMENT BV are set by an external device and used as flags for interrupt requirements. They are transmitted from an external device through inputs 29 and 30 (FIGURE 1). Typically, the signals AB Requirement and the Requirement BV are generated by the corresponding triggers in the external device, which are set up when service is needed, and are reset by DATA INPUT and DATA OUTPUT B,

Signal BV REQUIREMENT from the input 30 of the device (Fig. 1) enters the block

886

10 interrupts and 8 channel transmitters to one of the inputs of the transmitter 111. When a strobe signal enters the OB from the descrambler 3, another signal appears at the output of the transmitter 111, which arrives on the data bus 12 and is used by a computer analysis of the source of the interruption (FIG. 9).

The signal REQUIREMENT AB from input 29 goes to block 10 and to one of the inputs of multiplexer 4 (FIG. 5). If there are high levels of signals ADR01N and ADR02N, the signal REQUIREMENT AB goes through multiplexer 4 to block 6 and when an input signal comes in one of the inputs of the element NE-101 (FIG. 7) is transmitted via transceivers 104 to

data bus 12 (signal KD07N),

Register 9 is cleared by the initial setup signal RESET H (in FIG. 1, this signal is not shown), Interrupt unit 10 (FIG. T1 and 12)

performs channel control transfer via channel request signals. Block 10 consists of two unrelated parts, with the priority of the second part of the top priority

the first part.

Consider the work of the first part (Fig, 11),

Channel request - KEK signal (1) H is formed when signal interruption appears at the input of block 10 BW REQUIREMENT from an external device and BW RESOLUTION from register 9, This signal goes to a computer channel as an KZK4H signal via output bus 20

(the device has a 4th

interrupt level) In response to the appearance of a KZK4H signal on the channel, the computer sets to the channel (bus 19) the CDC 4B channel assignment signal (FIG. 1),

which is fed to the input element 164 of the second part.

Since the channel request is generated by the first part, the high level of the PDA 4B signal is transmitted to the output

PC (2) OUTPUT B (169, FIG, 12), so at the D-input of the trigger 172 presence-. There is a low level. Reset trigger 172 occurs on the trailing edge of the ignition PDA 4B.

The PDA signal (2) OUTPUT B comes in and the input of the element OR-NOT 127 of the first part (Fig. 11) as a signal of the PDA (1) move 8 and through the elements OR-NO 127 132 goes to the C-input of the trigger

142, on. The D input which is low. The trigger 142 of its state does not change even at the output of the element NOT-OR 133 (PDA (1) EXIT B) a low level. Thus, when a device requests a channel with this device, block 10 receives a PDA 4B signal over bus 19 and blocks its transmission to the next device.

When a PDA signal appears (1) INPUT B at the input of an OR-NOT 127 element, the interface device, if it has requested a channel, should remove the KNK 4H channel request signal, form

It can also be produced when a high level signal appears at the input of an OR-NOT 130 element, which indicates that the device has transmitted its data.

The work of the second part is basically similar to the work of the first part (Fig. 12).

When a signal interrupt appears at the input of the 10 fO unit, the AV REQUIREMENT from an external device and the AV RESOLUTION from register 9 generates a KPC request signal (2 I.). This signal enters the channel through bus 20

and transmit a response signal to the channel, 5 computers each as a KPC 4H signal (a device confirming selection (CWP H on the interface bus has the 4th interruption level). In response to the appearance of a KNC signal, the 4H computer exposes

21), at the occurrence of which the computer removes the channel signal of the PDA 4B on the bus 19 (Fig. 1).

The low level on bus 21 (signal 20 of laziness. Channel KPK 4B, which is post-CPV H at the output of element 118, 11) is fed to the C input of the trigger 172 (via

channel (on bus 19) signal provision elements 164 and 168). There is a high level at the D input of trigger 172 (through elements 149, 160, 25,137, 121), and the trigger will remain in

according to Wits, when the trigger 143 is set to a single state at the C input, to which the delayed leading edge of the PDA signal (1 (Input B, element 127, 136, 131, 134) arrives. In this case, a low level is present at the D input, since the trigger 142 is in the zero state and the PDA signal is present (1) INPUT B.

When the trigger 143 is set to one state, one of the inputs of the AND-NE element 117, which forms the KPC signal (1) H, causes a low level (via element 125), which will prohibit the transmission of the channel request signal to the computer.

A high level from the single arm of the trigger 143 enters the D input of the trigger 144. When a difference from a low level to a high at the C-inlet occurs, the trigger 144 becomes single, as a result, on the 18K KZN bus, the low level

elements 164 and 168). There is a high level at the D input of trigger 172 (through elements 149, 160, 25,137, 121), and the trigger will remain in

zero position. Further transmission over the PDA bus is blocked.

By the signal of the PDA 4B, trigger 173 will be set to one, so 30 is low at the B input of the trigger.

At the same time, the low level on the CPV H bus is shown and the channel request will be cleared (via elements 161 and 156).

The computer receives on the bus 21 signal KPVN and resets the signal on the bus 19 PDA 4V. In this case, the trigger 174 will be set to one when the signals associated with the previous data transmission will be cleared on the CKZ N and KSPN buses, and a low level is applied to the 18 KKZN bus.

After completing the cycle of connecting to the channel and generating signals

35

40

50

(through element 119). At the C-input of the Trig- 45 ° ™ KKZ N block 10 interrupts hera 144, a high differential occurs after a reset of the PDA signal (1) INPUT B, if there are no signals on the KZN and CPS H buses (i.e., there are high levels) related to previous data transfer.

When a trigger 144 is set to one, the low level of the zero-arm low resets the trigger 143 (via elements 123, 114, 141). The flip-flop 144 is reset when the signal circuit is removed at the input of the BV REQUIREMENT and BV RESOLUTION, and

55

causes program interruption, i.e. generates a signal to the SPR N (via element 120-1) on bus 31, and also generates the signals VEK N (via element 120-2) and VEK BV received in block 4. The vector VEK BV BV is generated in the case of a channel request by the first part.

The exchange of information between the computer Electronics-100/16 and the device is carried out through software operations with flag polling or software operations using program interruption tools.

It can also be produced when a high level signal appears at the input of an OR-NOT 130 element, which indicates that the device has transmitted its data.

The work of the second part is basically similar to the work of the first part (Fig. 12).

When a signal interruption appears at the input of block 10, the AV REQUIRES AV from an external device and the AV RESOLUTION from register 9 generates a request signal of the KPC channel (2 I.). This signal goes to the channel via bus 20

A channel (on bus 19) is a signal of the provision of a PDA 4B channel, which enters the C input of trigger 172 (via

elements 164 and 168). A high level is present at the D input of trigger 172 (through elements 149, 160, 137, 121), and the trigger will remain in

zero position. Further forward, the clock on the PDA bus is blocked.

By the signal of the PDA 4B, trigger 173 will be set to one, since the low level is present at the B input of the trigger.

At the same time, the low level on the CPV H bus is shown and the channel request will be cleared (via elements 161 and 156).

The computer receives on the bus 21 signal KPVN and resets the signal on the bus 19 PDA 4V. In this case, the trigger 174 will be set to one when the signals associated with the previous data transmission will be cleared on the CKZ N and KSPN buses, and a low level is applied to the 18 KKZN bus.

After completing the cycle of connecting to the channel and generating signals

50

45 ° ™ KKZ N block 10 interruptions

55

causes program interruption, i.e. generates a signal to SPR N (via element 120-1) on bus 31, and also generates signals VEK N (via element 120-2) and VEK BV received in block 4. The vector VEC BV is formed in the case of a channel request by the first part.

The exchange of information between the computer Electronics-100/16 and the device is carried out through software operations with flag polling or software operations using program interruption tools.

9

For addressing devices are used the last 4K address space of the computer Electronics-100 / 16I, i.e. addresses from 7600008 to 7777778,

The device is represented by the computer as three addressable registers with the following addresses: status register 7XXXXO, output buffer 7XXXX2, input buffer 7XXXX4, X set by the user.

The 9 state register has 6 bits. Four of them can be downloaded and read programmatically. These are bits of the RSOO and PC-01, which can be used to simulate interrupt request requests in the offline scan mode, and bits of the RSOb and PC05 (PERMISSION AB signals and BW SOLVING), which control the logic of the device.

The two bits PC07 and PC15 (signals REQUIREMENT AB and REQUIREMENT BV, respectively) of register 9 of the state can only be read by software. Signals REQUIREMENT AB and REQUIREMENT BV are set by an external device and used as flags for interrupt requirements. Usually they are generated by the corresponding triggers in the external device, which are set up when service is needed, and are reset by the DATA INPUT signal and the DATA OUTPUT signal B. The format of the register 9 and the STATUS REGISTER is shown in FIG. 13.

The device is capable of storing 16 bits of one output word of two output bytes in register 7, OUTPUT BUFFER. Recorded data in the output buffer (VDOOV-VD15V) is transmitted via a communication cable to an external device. Any software operation that loads a byte or word into the output buffer causes the signal DATA OUTPUT B to inform the external device about the data transfer. The output buffer can be read programmatically. The format of the register 7 OUTPUT BUFFER is shown in FIG.

The input data (WWOOV-VB15V) is transmitted to the computer data bus 12 during the data entry operation. All 16 bits are placed on the computer data bus 12 simultaneously. When executing a computer byte instruction, it uses only the most significant or the least significant byte. When data is read by a computer, a DATA INPUT signal B is generated,

810

which is sent to an external device to inform the latter about data reception. The format of the ENTRY BUFFER register is shown in FIG. 13.

The device works as follows (Fig. 1).

Computer Electronics-100 / 16I, referring to the device, places the address on the bus 13 (signals KUDR, KADR17N)

and the operation code on bus 15 and 16 (signals KV / VON and KV / V1N) (respectively), and then on bus 14 - the synchronization signal of the active device

(XAN signal). Signals indicated

arrive at block 1 of channel receivers, from the output of which the signals ADROSV, ADR12V, ADR14F, ADR13V, ADR16; ; ADR15V, SALADR17V come on de.

encoder 2 addresses. The address decoder, 2 decodes the address and when the address transmitted by the computer coincides with the address of the interface device dialed by K1 K2 switches, produces a high level signal DEVICE SELECTED that permits the operation of the decoder 3 control signals. When a signal arrives, the DEVICE IS SELECTED on the decoder 3

the latter, depending on the combination of signals ADROOV, ADR01V, ADR02V, B / B1B, B / BOB, generates the corresponding signals controlling the internal valves of the interface device and the output signals of the DATA INPUT and OUTPUT OF DATA B for the external device, arriving respectively at tires 28 and 27 are listed in table. 1. With the delay required

For the coupler to perform a predetermined mode of operation, the decoder 3 of the control signals also generates a synchronization signal of the passive device K SPN, fed through bus 17 to the computer.

During the operation of an external device with a computer through a interface device, the following main modes of operation are possible: input of information into a computer, output

information from the computer, the formation of signals for interrupting programs for maintenance. external device.

Consider the operation of an interface device in each of the listed

modes.

Enter information into the computer from an external device. Entering information into the computer from an external device is carried out

through the input buffer, which is a 16-bit gate register. It includes the screw transmitters of channel transmitters of blocks 5 and 6 of channel transceivers, which transmit data from an external device to a computer channel under program control (Fig. 1).

The low data byte from the external device (WWOOD-BB07B) is transmitted to the computer via the multiplexer 4 and the channel transceiver unit. When the interface device is operating in this direction, the control inputs of multiplexer 4 from the decoder 3 control signals receive a high signal level ADR01N and a low signal level ADR02N, and the output from multiplexer 4 passes information from an external device (see Table 2).

The highest data byte from the external device (BB08B-BB15B) is transmitted to the computer directly through the block 5 channel transceivers.

The data is entered into the computer during the data entry operation, in which the decoder 3 generates the signals INPUT 4H and DATA INPUT B.

The 4H INP signal is gated-ZO cut blocks 6 and 5 channel transceivers for blocks 5 and 6 channel transceivers. During the operation of this pulse, data from the external device is placed on the data bus 12. After the data is installed on the bus 12, the interface device generates the SPFC signal, which is fed through the bus 17 to the computer. The computer, having received on the bus 17 the signal KSPN, reads data from the bus 12 data and removes the signal KSAN, as well as signals KV / V1N and KV / VON. After the XAN signal is removed in the interface, the signal generated by the 2 address decoder is removed, the DEVICE IS SELECTED and the operation of the decoder 3 control signals is prohibited. Data is removed from. tires 12. Disconnection of a signal DEVICE SELECTED causes the removal of the signal of the SPF, which indicates the computer to complete the operation of entering information into the computer. Since the input buffer does not store information, it is external. the device must hold the input data on the signal lines of bus 24 (BB08B-BB15B) until the input is completed. When entering information into the computer, the decoder 3 of the interface generates a DATA INPUT signal,

35

40

Editors on buses DOOV-D07V and DOV8-D15V to the inputs of the output buffer 7. The lower data byte from the computer to the output buffer register 7 enters through block 6 channel transceivers, high byte through block 5 channel transceivers. The computer then exposes a XAN signal to bus 14.

After that, the address is decoded by the decoder 2, the signal is generated; the DEVICE IS SELECTED and the corresponding signals are generated by the decoder 3 control signals

45 is similar to that described.

The data output from the computer is carried out during the data output operation, in which the decoder 3 generates the signals O 2BMB, O 2CBV,

50 DATA OUTPUT B. Signals 2MBV OUT and S2SB OUT are gate signals for writing to output buffer register 7. During the output operation, both signals are strobed Data from

55 internal lines D008-D15B into the register 7. When the byte operation is performed, only one of these two signals gates the data to the corresponding part of the output register 7, which is defined via bus 28 to the external device. On the falling edge of this pulse. Input data can be removed by an external device.

DATA INPUT signal B is active during an input operation when a read operation is performed from the input buffer. By connecting the capacitance 92 to the pulse delay pulse shaping circuit, an increase in the pulse width of the DATA INPUT B signal is possible.

Information output from a computer to an external device. Information output from a computer to an external device is carried out through the output buffer register 7, consisting of two 8-bit registers, which allow the output of 16-bit words or 8-bit bytes.

The transfer of information from the computer is as follows.

The computer sets the transmitted data (signals of KDOO 15N) on the busbars 12 data, the address of the device (signals KADROO-17H) on bus 13 and the operation code of output to buses 15 and 16 (signals KV / VON and KV / V1N), respectively). The data from the computer from the bus 12 comes four

0

Editors on buses DOOV-D07V and DOV8-D15V to the inputs of the output buffer 7. The lower data byte from the computer to the output buffer register 7 enters through block 6 channel transceivers, high byte through block 5 channel transceivers. The computer then exposes a XAN signal to bus 14.

After that, the address is decoded by the decoder 2, the signal is generated; the DEVICE IS SELECTED and the corresponding signals are generated by the decoder 3 control signals

5 as described.

The data output from the computer is carried out during the data output operation, in which the decoder 3 generates the signals O 2BMB, O 2CBV,

0 DATA OUTPUT B. Signals 2MBV OUTPUT and OUTPUT S2SB are gating to write to output buffer register 7. During the output operation, both signals are gated Data from

5 internal lines D008-D15B to the register 7. When the byte operation is performed, only one of these two signals gates the data to the corresponding part of the output register 7, defined 13

The specified address is 00. The data is written to the output buffer register 7, from where it becomes available to the external device via buses 22 and 23.

After receiving the data in the output. The register 7 of the decoder 3 of the control signals generates a signal PSCP which through the bus 17 enters the computer. The computer, receiving the signal KSPN, removes from the bus 14 the signal KSAN, and then the data from the bus 12 data, and signals .KB / VON and KV / V1N from tires 15 and 16, respectively.

. After the XAN signal is removed in the interface, the signal DEVICE SELECTED, produced by the decoder 2, is removed and the operation of the decoder 3 control signals is prohibited. Deletion of a signal DEVICE SELECTED causes the removal of the KSPN signal from the bus 17, which indicates the computer to complete the output operation.

When the output buffer register

7 is loaded during the output operation or byte output, the decoder

3 control signals form a signal, DATA OUTPUT B, informing the external device that data will be transmitted to it. Rear of positive pulse. DATA OUTPUT

8can be used to build data in an external device.

The DATA OUTPUT signal B is active during the output operation when writing to the output buffer register 7. By connecting the capacitance 92 to the pulse-shaping circuit of the SPAC, the pulse width, the DATA OUTPUT signal can be increased.

If necessary, the output buffer register 7 can be read programmatically. To do this, you need to access it at 7XXXX2 in input mode. In this case, the computer places the address on the bus 13, the input operation code on buses 15 and 16. In this case, the control decoder 3 generates a low level of the ADR01H signal and a high level of the ADR02H signal, which go to the control inputs of the multiplexer 4. The multiplexer output 4 in this case passes the low byte information of the output buffer register 7 with buses VD08V-VD007V (Table 2), which is fed to the input of block 6

31598814

channel transceivers. The high byte of the output buffer 7 from the VD08V-VD15V buses goes directly to the input of a block of 8 channel transmitters.

c. Then the computer places the signal KSAN on the bus 14. The decoder 3 control signals in this case produces the signal ENTER 2H, which is the building block for channel 5

10 transceivers and block 8 channel transmitters. During the operation of this pulse, the information supplied to the inputs of blocks 5 and B is placed on the data bus 12. After this, the interface device generates a signal of the SPFC, which is fed via bus 17 to the computer. The computer, having received this signal, reads the data from the bus 12 and removes the signal KSAN, as well as signals KB / BtH

20 and KV / VON.

After the XAN signal is removed in the interface, the signal from the decoder 2 addresses is removed, the signal DEVICE IS SELECTED and the operation of the decoder 3 control signals is prohibited. The data is removed from the bus 12. Deactivation of the signal The DEVICE SELECTED causes the removal of the signal of the SPAC, which indicates the computer to complete the transfer of the transfer of information input to the computer.

Formation of program interrupt signals. The interface device contains interrupt logic that is compatible with the Electronics channel 35 100 / 16I computer channel, which allows the external device to generate interrupt requirements.

With the help of two independent signals, the requirement of the AV and the requirement of the BV,

40 arriving at inputs 29 and 30, respectively, an external device can request a program interruption from a computer via two separate interrupt vectors. In addition, two digits

45 of the register of the 9th state PERMISSION AB and PERMISSION BV (signals of the PICNB and the PWPRB) independently or not allow the transmission to the computer of the corresponding requirements of the NIN 50, coming from an external device. The presence of interrupt requirements can be determined by a computer based on the state of the PC07 and PC15 signals of register 9. Since each demand of an interrupt corresponds to an eigenvector, one of the requirements can be used to indicate that the external device data is ready for input into the computer channel. Other

The interrupt request can be used to indicate that the external device is ready to receive new information.

The channel request signal of KPC 4H on bus 20 is generated when interrupt enable triggers (A or B) in state register 9 are set and there is a corresponding interruption request from an external device.

In response to the appearance of the request signal of the SCK4N channel, the computer transmits a signal to the channel via the PDA bus B. When it appears, the interface device removes the request signal of the CPC4H channel, generates and transmits a response signal confirming the selection of the CWPH, at which the computer resets the channel signal on the CPKV bus,

Upon completion of the operations associated with the previous data transmission, the ACF and CCF buses are released (i.e., there are high levels), the interface device generates an ACC signal via the bus 18.

After completing the cycle of connecting to the channel and generating a signal on the bus 18KKN, the interface device generates the signals of the CENTRUM AND the CPRN.

The VEK N signal comes from block 10 to data multiplexer 4 (to elements 93 and 94). At the outputs of element 93 and 94, high levels are formed, which arrive at the address inputs of multiplexers 95, 98. At the same time, the information on the outputs of multiplexers 95-98 is transmitted from the DZ inputs of the indicated circuits (i.e., the outputs of data multiplexer 4 transmit information about the address of the interrupt vector - WUA).

The VEK N signal also enters the channel transceiver unit 6 and enables transmission of the interrupt vector address from multiplexer 4 data to the computer data bus 12.

In addition, the address of the interrupt vector can be incremented along the KD02N bus by a signal from the VEK BV. When an interruption from a signal occurs, the REQUIREMENT B is a high level BEC signal, and when an interruption from a signal is triggered, the REQUIREMENT AB is a low level.

The addresses of the interrupt vectors are selected in the address space 0.377 ,,: LLCXXO - interrupt A, LLCXX4 interrupt B, where X is set

user and dialed using the K4 switch,

Thus, on the data bus 12, the address of the interrupt vector is set and the CKPN signal is generated on the bus 31, at the same time, the device resets the TON H signal and transmits the CCH signal N.

The computer receives the CPRN signal, waits for 75 NS to compensate for the scatter in the CPRN arrival times and the address of the interrupt vector, receives the WUA and transmits the CSIF.

The interface receives CCFR and cleans the tires 37 of the CPRN, 12 data, 18 KKZN,. A computer channel transmission is active.

The computer resets the CPR signal, having received the CPRN reset, and enters the interrupt sequence to memorize the current contents of the CS command counter and the RSP processor status register and replace them with the interrupt vector of this device, in accordance with the normal operation of the computer.

Claims (1)

Invention Formula A device for interfacing a computer with an external device, comprising a block of channel transmitters, two blocks of channel transceivers, an output buffer register, an interrupt vector address register, a data multiplexer, a state register, an address decoder, a control decoder, and a group of information outputs block channel transmitters, groups of information inputs-outputs of the first and second blocks of channel transceivers form a group of inputs-outputs of the device for connection to the group and The computer information inputs / outputs, the first, second, third, fourth overhead outputs and the first interrupt request input of the interrupt unit are respectively the outputs and the device input for connecting to the channel occupation inputs, channel request, sample validation, puncturing and output of the computer channel output respectively, the first and second groups of information outputs of the output buffer register are connected to the group of information inputs of the channel transmitter unit and to the first group of information data multiplexer input inputs, respectively, and form device output groups for connecting to the first and second groups of information inputs of an external device, respectively, a group of information inputs of the first block of channel transceivers, and the second group of information inputs of a data multiplexer the outputs of the external device, the first and second outputs of the register. The states are the outputs of the device for connection to the first and The first and second outputs of the decoder control signals are the outputs of the device for connecting to the write and read inputs of the external device, respectively, the second interrupt request input of the interrupt unit is connected to the data input of the data multiplexer and is the device input for connecting to the first output an external device interrupt request, the third interrupt request input of the interrupt block is connected to the information input of the block cial transmitters and is an input device for connection to the second Leaving the interrupt request of an external device, the third output of the control decoder is connected to the synchronous input of the state register, the third and fourth output1 of which are connected to the fourth and fifth interrupt request inputs of the interrupt unit, respectively, the fifth output of service signals. which is connected to the first gating input of the channel hemopower transducer block and the first control input of the data multiplexer, the third group of information inputs of which are connected to the first, second, third and fourth state register outputs, group of information inputs which is connected to the group of information outputs of the second block of channel transceivers and with the first group of information inputs of the output buffer register, the second group of information inputs, which is connected to the group of information outputs of the first block of channel transceivers, gating 50 Q five five 0 . the input of which is connected to the second building input of the second channel transceiver unit and to the fourth output of the control signal decoder, the fifth output of which is connected to the third gate input of the second channel transceiver unit and to the first gate input of the channel transmitter unit, the second gate input of which connected to the sixth output of the decoder control signals, the seventh, eighth, ninth, tenth and eleventh outputs of which are connected to the fourth gate input of the second block channel channel transceivers, the first, second synchronous inputs of the multiplexer data, the first, second synchronized inputs of the output buffer register, the output group of the interrupt vector address register register is connected to the fourth group of information inputs of the data multiplexer, the group of information outputs of which is connected to the group of information inputs of the second channel transceiver unit, The address of the address decoder is connected to the enable input of the control decoder signals, characterized in that, in order to expand the Due to the use of separate address and data buses, a block of channel receivers is entered into it, the group of information inputs of the channel receiver block forming the second group of device inputs for connecting to the address outputs of the computer, the first and second information inputs and the gate input of the channel receiver unit the inputs of the device for connecting to the first, second outputs of the operation mode and the synchronous output of the computer, respectively, the twelfth output of the control decoder is connected to The sixth interrupt request input of the interrupt unit and is the output of the device for connecting to the synchronous input of the computer, while the sixth output of the interrupt unit service signals is connected to the second control input of the data multiplexer, the first and second groups of information outputs of the channel receiver unit are connected to the groups of information inputs of the address decoder and a control decoder, respectively. X is an indifferent state. /four SbifpOHO To the decoder 3 Device SbifpOHO Decoder 3 Fig.Z From Deshi Rtoraz WI Ш2. Fi & b rv : "3 7th session 66 from the external system, yes RSod OB from decoder 3 FIG. 9 Requirement 66 from the outside mouth, yes Permission from Reis / PR 9 . & P fxeftu / f3 L1 from aefibi W9 /. about Physical Institute cnt to TpeffoSaMue AB external device - 0s / vi f jpeuieHueA off register From cxeffut P6 18 CNZN 7 NOLN k & k1g) n ffl hpkYubyhozhody "Rig.K (43nUDflUinhj) OOOd (Q nUDS / WTthO) 3d (QznuDe / shnhe) 9 HHBfn dSVd (f:} nuoe / uinho) y HHmjdSVd (dpnt) d1 sppe) y nHVSOQJdl (elnodyushpne) 93HHV80g dl Editor N. Gunko Compiled by S. Pestmal Tehred M. Khodanich Proofreader M. Demchik 2364/51 . Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4