SU1480123A2 - Binary code reversible generator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in various schemes of digital automation, in particular, in schemes for controlling the position of the marker mark of the indicator device. The purpose of the invention is to expand the functionality of the imaging unit by ensuring the formation of two operating ranges (or one operating range with an internal region of unacceptable conditions). The shaper contains a reversible counter, four AND-NES elements, two triggers, groups of elements AND, a group of elements OR, and a logic unit whose output is fed to the input of the installation of the reversible counter in a valid state defined by the code from the outputs of the group of elements OR to which the signals arrive from the outputs of the groups of elements I. AND-NOT provide control of the achievement of the specified boundaries, blocking further counting and controlling the triggers, which by their output signals control the operation of the logic unit. 1 il.

Description

one

The invention relates to a pulse technique and can be used in various schemes of digital automation, in particular, in schemes for controlling the position of the marker mark of the indicator device.

The purpose of the invention is to expand the functionality by providing two ranges of generated codes.

The drawing shows a flowchart of a reverse binary coder (for a four-bit counter).

The reverse binary shaper contains a reversible counter 1, the first 2 and the second 3 elements K-NOT

and element 4, the output of which is connected to the clock input of the reversible counter 1, whose outputs corresponding to the first maximum and first minimum generated codes are connected respectively to the inputs of the first 2 and second 3 AND-NOT elements whose outputs are connected to the inputs of the AND 4 element The first 5 and second 6 control buses are connected respectively to the input of the add permission and the enable input of the subtraction of the reversible counter 1, which are connected to the additional inputs of the first 2 and second 3 AND-NOT elements, respectively and the first additional input of the AND 4 element is countable

Ј

00

i

14)

input 7 of the reverse binary binary coder, as well as logic block 8, containing AND 9-12 elements, the inputs of each of which are connected to the outputs of the reverse counter 1 for decoding invalid states, and the outputs of AND 9-12 elements of the logic block 8 are connected to the inputs

N-NOT, respectively, the first and second lower limit of the account - codes of numbers 2 and 5, respectively. Element And with 9 logical block 8 is connected to

direct outputs 2–4 bits (high) of counter 1, i.e. tuned to the numbers 14 and 15, the element AND 10 - to the inverse outputs 2 and 3 bits and etc. - the element OR 13, the output of which is to the jQ output of the 4 bits, i.e. tuned to the inputs of the reversing installation - the number 8 and 9, the element AND 1I - to the direct counter 1 in the permissible state of the outputs 2 and 3 bits and inverse. In addition, the reversible form-fed output of 4 bits, i.e. the tuner contains the first 14 and second enters for the numbers 6 and 7, the element AND 12 - to 15 groups of elements AND, the group of elements 15 inverse outputs of 2–4 bits, i.e. 16, third 17 and fourth 18 are set to the numbers 0.1. On the first 21 cops, the IS-NOT and the first 19 and second 20 triggers, the inverse outputs of which are connected to the additional inputs of the OR element 13 of the logic unit 8, the clock inputs - with the counting input 7 of the reversing driver of the binary code, and the D-inputs - corresponding to the second 22 code The tires are given the second upper and lower counting codes, respectively, i.e. numbers

20 10 and 5 „

Suppose that at some point in time the enabling signal arrived at the addition bus 5, the counter 1 was in the state of the number 2, i.e. at

with the second and third additional inputs of the AND 4 element, with its S-inputs, as well as with the outputs of the third 17 and fourth 18, respectively, AND-NOT elements, whose inputs are connected to the reverse outputs

but, and the additional inputs, respectively, with the resolution of the resolution of the calculator 1, corresponding to the second 30, the output of the counter 1 forms the maximum and the second minimum code of the number 5, and the fourth element IS-NOT 18 is activated and

the output level appears, the blocking element AND 4 and the incoming and the input resolution of the addition of 35 shu to the D input of the second trigger 20, the reversible counter 1, the information of which is simultaneously set to the inputs of the 16 The first and second inputs of which are connected to the outputs of elements I, respectively, of the first 14 and second 15 groups, respectively, the first inputs of which are connected respectively to the first 5 and second 6 control buses, and the second to the first 21 and second 22 groups — 45 are recorded code number 10 (with mi code buses reversible form the first group of code buses 21 through the binary code pad, respectively, elements AND 14 of the first group and the element operation of the device will be looked at you OR 16 groups according to its informational example of four-bit reversible inputs). At the output of the fourth counter, for which the working 5Q element of AND-NE 18 forms a unit, the range is determined by the numbers from 2 to the level, the unlocking element 13 and has unacceptable conditions O, 1, 14, 15 external areas of numbers and 6-9 internal areas. At the same time

the first 2 and the third 17 elements K-KE 55

first and second respectively

the upper limit of the account dialed codes

numbers 13 and 10 respectively, and on

second 3 and fourth 18 elements

from his S-input. With the arrival of the fourth counting pulse on bus 7, the second trigger 20 at the clock input is zeroed, after which the unit level from its inverse output through the OR element 13 of the logical block 8 ° enters the input of the installation of the reversible counter 1, in which

And 4 and setting the second trigger 20 on the S-input to the single state, remove the code writing mode into the counter 1. After receiving 5-7 counting pulses, the contents of the counter 1 become equal to the number 13, the first element K-HE 2 is triggered and the generated at its output, NLEH does NOT, respectively, of the first and second lower count limit — codes of numbers 2 and 5, respectively. Element And 9 logical block 8 is connected to

direct outputs 2–4 bits (high) of counter 1, i.e. set to numbers 14 and 15, element 10 and 10 to the inverse outputs 2 and 3 bits, and so forth — to my output 4 bits, i.e. it is set to numbers 8 and 9, element 1i to direct outputs 2 and 3 bits and inverse output 4 bits, i.e. tuned to the numbers 6 and 7, the element And 12 - to 5 inverse outputs of 2-4 bits, i.e. tuned to the numbers 0.1. At first 21

direct outputs 2–4 bits (high) of counter 1, i.e. tuned to the numbers 14 and 15, the element 10 and - to the inverse outputs 2 and 3 bits and the forward output 4 bits, i.e. it is set to the numbers 8 and 9, the element 1 1I - to the direct outputs 2 and 3 bits DOV and inverse output 4 bits, i.e. tuned to the numbers 6 and 7, the element And 12 - to the inverse outputs of 2-4 bits, i.e. tuned to the numbers 0.1. At first 21

and the second 22 code buses are given the codes of the second upper and lower limits of the account, respectively, i.e. numbers

10 and 5 „

Suppose that at some point in time the enabling signal arrived at the addition bus 5, the counter 1 was in the state of the number 2, i.e. at

the operating range of numbers, and the input 7 receives counting pulses that, through the element 4, arrive at the clock input of the counter 1. After the arrival of the third counting pulse

the output appears zero, the blocking element AND 4 and arriving at the D input of the second flip-flop 20, simultaneously removing the installation signal, recording the code of the number 10 (from the first group of code buses 21 through the elements 14 of the first group and its elements S With the arrival of the fourth counting pulse on the bus 7, the second trigger 20 at the clock input is zeroed, after which the unit level from its inverse output through the OR 13 element of the logic block 8 is fed to the input of the reversible counter 1, in which

you OR 16 groups by its information inputs). At the output of the fourth element AND-NOT 18, a unit level is formed, unlocking the element

And 4 and setting the second trigger 20 on the S-input to the single state, remove the code writing mode into the counter 1. After receiving 5-7 counting pulses, the contents of the counter 1 become equal to the number 13, the first element K-HE 2 is triggered and the generated at its output, the zero level blocks element 4. Thus, the device has sequentially formed code combinations of numbers 2–5, 10–13, and is in the state of the first upper limit of light, i.e. in the state of the number 13.

Element 4 is unlocked only when the resolution of the counting direction is changed. In this case, the counter code 1 begins to decrease and the operation of the device is similar to that described above, but the third element AND-NOT 17 and the first trigger 19 are controlled by the operation, and the code in counter 1 is recorded from the second group of code buses 22 through elements 15 of the second groups and elements OR 16 groups. When the code of number 2 is formed at the output of counter 1, the second element IS-HE 3 is triggered, which will block the passage of counting pulses to the clock input of counter 1.

Thus, the counter code 1 can vary in the range of numbers 2-5 10-13.

If during the initial switch-on or under the influence of interference in the counter 1, the code of one of the invalid numbers (0,1,6-9,14,15) appears, then the corresponding AND 9-12 element of the logical block 8 and the signal from its output Passing through the element OR 13, writes to the counter 1 of the working range number, i.e. the numbers 5 or 10 (depending on the availability of the permission signal for subtraction or addition, respectively).

If on the first 21 and second 22 groups of code buses, and consequently, on the IS-NOT elements 18 and 17, to set the codes of the preceding and subsequent (for the time being) numbers, respectively, the device will form a group of consecutively following

14801236

code combinations within the range of about

Formula Invention

Reverse binary shaper auth.St. N 1257844, characterized in that, in order to extend the functionality by providing two ranges of generated codes, the first and second groups of elements AND, the group of elements OR, the third and fourth elements of AND-NOT and the first second triggers are introduced into it, the inverse outputs of which connected to the additional inputs of the OR element of the logic block; clock inputs are connected to the counting input of the reversing binary code generator, and the D- inputs are connected respectively to the second and third additional inputs of the AND element, Our S-inputs, as well as with the outputs of the third and fourth AND-NOT elements, respectively, the inputs of which are connected to the outputs of the reversible counter corresponding to the second maximum and second minimum generated codes, respectively, and the additional inputs to the subtraction resolution input and the resolution input adding a reversible counter, the information inputs of which are connected to the outputs of the elements OR of the group, the first and second inputs of which are connected to the outputs of the elements of the same name AND respectively oh and second groups, the first inputs of which are connected to the first and second control lines respectively, and the second - the first and second groups of code shaper tire reverse binary code, respectively.

Claims (1)

_ The claims of Reversible binary code former No. 1257844, characterized in that, with 10 to expand functionality by providing two ranges of generated codes, the first and second groups of AND elements, a group of OR elements, the third and fourth AND elements and the first and second triggers whose inverse outputs are connected to additional element inputs are introduced into it OR of a logic block, the clock inputs are connected to the counting input of the reverse generator of the binary code, and the D inputs are connected respectively to the second and third additional inputs of the I element, with their B-inputs 25 and also with the output odes of the third and fourth AND-NOT elements, respectively, whose inputs are connected to the outputs of the reversible counter corresponding to the second maximum and 30 second minimum codes respectively formed, and additional inputs - respectively to the enable input of subtraction and addition of reverse enable input COUNT ^- 35 ka, the information inputs of which are connected to the outputs of the elements OR groups, the first and second inputs of which are connected to the outputs of the same elements AND, respectively, the first and second groups, the first inputs of which are connected to the first and second control buses, respectively, and the second to the first and second groups of code buses of the reverse generator of the binary code, respectively.