SU1457159A1 - Pulse train monitoring device - Google Patents

Abstract

The invention can be used in automation and to control the nodes of digital computing devices. The purpose of the invention is the expansion of the field of application due to the possibility of controlling the sequence of pulses with monotonously changing the follow-up period - is achieved by introducing the device element OR 14, the element NOT 15 and new connections, the device also includes the input bus 1, the element And 2, pulse generator 3, counter 4, delay elements 5 and 6, pulse generator 7, register 8, subtraction block 9, comparison block 10, code setting bus 11, AND-NOT elements 12 and 13, trigger 16, output bus 17 . Introduced differences provide the opportunity ozhnost indicating the occurrence of a priori unknown input sequence of pulses with monotonically varying repetition period. 2 Il. p s ate sd | ate with

Description

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The invention relates to a pulse technique and can be used in automation and for controlling nodes of digital computing devices.

The purpose of the invention is the expansion of the field of application due to the possibility of controlling a sequence of pulses with a monotonically varying follow-up period.

Figure 1 shows the block diagram of the device; Fig. 2 is a block diagram of a subtraction unit.

The device for controlling the pulse train (Fig. 1) contains an input bus 1, element II, pulse generator 3, sensor 4, delay elements 5 and 6, pulse driver 7, register 8, subtraction unit 9, comparison unit 10, -shire 11 set the code, the elements AND-NOT 12 and 13, the element OR 14, the element NOT 15, the trigger 16 and the output bus 17.

The output of the element IS-HE 13 is connected to the installation input to the unit trigger 16, the output of which is connected to the output bus 17, the input bus I is connected to the input of the driver 7, the first group of inputs of the subtraction unit 9 is connected to the outputs of the counter 4, to the information inputs of the register 8, the outputs which is connected to the second group of inputs of the subtraction unit 9. The outputs of which are connected to the first group of inputs of the comparison unit 10, the second group of inputs of which are connected to the code setting buses 11, the output of the driver 7 is connected to the input of the delay element 5 and and the inputs of AND-NO elements 13 and 12, second inputs of which are connected respectively to the outputs of Equals unit 10 and comparing the output of the OR gate 14 which is connected via a NOT element 15 to a third input of AND-NO element 13.

Output More or less of the comparison unit 10 is connected to the first input of the element OR -14, the second input of which is connected to the output Sign of the sign of the subtraction unit 9. The output of the NAND 12 is connected to the input of the zero setting of the trigger 16, the output of the delay element 5 is connected with the clock input of the register 8 and with the input of the delay element 6, the output of which is connected to the reset input of the counter 4, the counting input of which is connected to the output of the element I 2, the direct and inverse inputs of which are connected respectively

with the output of the generator 3 pulses and input bus 1.

Block 9 subtraction (figure 2) contains the first adder 18, the first block 19 of inverters, the switch 20, the second block 21 of inverters and the second adder 22. The first group of inputs of the block 9 subtraction (input reduced) is connected to the inputs A of the adder 18, the second group of inputs Block 9 of the subtraction (input of the subtracted) is connected to the inputs of block 19 of the inverters, and the output is connected to the output of the switch 20, Leader bit C. J. cyMNb:, formed by the adder 18, forms the output Sign of the sign of the block 9 of the subtraction.

The device works in the following manner.

The controlled pulse sequence is fed to the inverse input of the element And 2 and the input of the imaging unit 7 pulses. The second group of inputs of the comparison unit 10 receives a driver code for buses 11, which determines the accuracy of monitoring the pulse pulse period. Element I 2 opens when a zero logic level appears at its inverse input. Thus, the pause between two pulses of the sequence is filled by the pulses of the generator 3. The code formed at the outputs of counter 4 and the code set at the outputs of register 8 are transmitted respectively to the first and second groups of inputs of subtraction unit 9.

The first adder 18 and block 19 of the inverters form the difference between the codes supplied to the first and second inputs of block 9. For this, the code fed to the second input of block 9 is converted by the block 19 of inverters to inverse and the feed to the transfer input P of the adder 18 unit converts it to an additional . In this case, a logical zero is applied to the input of the high bit of the first code of the adder 18, and a logical one is fed to the input of the high bit of the second code, which subtracts the second code from the first. The highest bit of the sum indicates which sign has the difference, forming by the adder 18. If the highest bit of the difference (signed C p) is zero, then the difference is positive and through the switch 20 the output of block 9 receives the module of the difference of codes, i.e. all bits of the difference, except the senior. Her10

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If the most significant bit of the difference between the output of the adder is 18 is one, the difference is negative and is presented in the additional code. At the same time, this code comes from the output of the adder 22 through the switch 20 to the output of the subtraction unit 9. Using the inverter unit 21 and the adder 22, the additional code is converted into a direct code.

The difference modulus is compared in block 10 of comparison with the code received via bus 11. If the difference between two successive pauses is positive (at the output, the sign of the sign is logical zero) and is equal to the specified value (high logical level at the output is equal to block 10 of comparison), then the impulse produced by the shaper 7 is fed to the S input of the trigger 16 and confirms a high logic level on the output bus 17 of the device. The same impulse with a delay generated by elements 5 and

My counter 4 is in register 8 and resets counter 4. If there is a negative difference between the pauses (logical unit at output Sign of the sign of block 9) or different from the set value (logical unit at output More or less than block 10), trigger 16 is reset.

Thus, the proposed device monitors monotonically increasing sequences. To monitor monotonously decreasing sequences, the input of the element OR 4 switches to the inverted output of the sign of the subtractor 9.

pulses, two delay elements, the And element, the trigger, the code setting bus, the output bus, and an input bus connected to the input of the pulse former and the inverse input of the And element, whose direct input is connected to the output of the clock generator, and the output to the counting input the counter, the outputs of which are connected to the first group of outputs of the subtraction unit and the inputs of the register, the outputs of which are connected to the second group of inputs of the subtraction unit, the clock input of the register is connected to the input of the second delay element, the output of which is connected to the input reset the counter and the output of the first delay element kotog cerned input connected to the output pulse shaper and the first inputs of first and second AND-NO elements, the second input of the first AND-NO element is connected to the first output unit srav30

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the first group of inputs

6 delay, rewrites the contents- 25 is connected to the outputs of the subtraction unit,

and the second group of inputs - with the code setting bus, the outputs of the first and second elements AND-NOT are connected respectively to the input of setting the single and zero state of the trigger, the output of which is connected to the output bus, characterized in that control of a pulse train with a monotonically varying period of time, the element is NOT entered and the element OR is whose first input is connected to the input. The sign of the subtractor block sign, the second input is compared to the second output of the block. and the output with the second input of the second NAND element and the input of the NO element, the output of which is connected to the third input of the first NAND element, the first output of the comparison unit being the Equals output, and its second output is the Output More or less.

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Claims (1)

Invention Formula A device for controlling a sequence of pulses, comprising a pulse generator, a counter, a subtraction unit, a comparison unit, two NAND units, a register, a driver 0 five 0 pulses, two delay elements, the And element, the trigger, the code setting bus, the output bus, and an input bus connected to the input of the pulse former and the inverse input of the And element, whose direct input is connected to the output of the clock generator, and the output to the counting input the counter, the outputs of which are connected to the first group of outputs of the subtraction unit and the inputs of the register, the outputs of which are connected to the second group of inputs of the subtraction unit, the clock input of the register is connected to the input of the second delay element, the output of which is connected to the input reset the counter and the output of the first delay element kotog cerned input connected to the output pulse shaper and the first inputs of first and second AND-NO elements, the second input of the first AND-NO element is connected to the first output unit srav30 45 35 45 45 40    "0 tY Y .i.   "Tf TT "SI   "0 tY .i.