SU1363424A2 - Frequency multiplier - Google Patents

Abstract

The invention relates to radio engineering. In relation to aut. St. No. 1148088, the objective of the invention is achieved - to increase the frequency multiplication accuracy. Frequency multiplier contains frequency dividers 1 and 5, counter 2, reversible counter 3, comparison block 4, triggers 6 and 7, e-mails OR 8 and 10, zl-you 9 and 11, and prohibition e-mail 12 and 13. Purpose This is achieved by providing a reduction in the malfunction of the frequency multiplier with the help of the injected inhibitors 12 and 13. 1 sludge. from 05 WITH 4 HS 4 MS

Description

The invention relates to radio engineering and can be used to multiply the frequency in the equipment for receiving and transmitting information and in the synchronization systems of computer devices and is an improvement of the invention according to the author. St. No. 1148088.

The purpose of the invention is to improve the frequency multiplication accuracy by reducing malfunctions.

The drawing shows a structural electrical circuit of the proposed frequency multiplier.

The frequency multiplier contains the first frequency divider 1, counter 2, reversible counter 3, comparison unit 4, second frequency divider 5, first trigger 6, second trigger 7, first element OR 8, first element 9, second element OR 10, second element II 11, the first element of the ban 12, the second element of the ban 13.

The multiplier works as follows.

When the start signal is given. At one of the inputs of the second element 11, the signal of the input frequency f through the second element I1 sets the counter 2 to the initial state, the first and second dividers 1 and 5, the reversing counter 3 and the second trigger 7. The signal of the reference frequency f is fed to the counter 2 When the output codes of counter 2 and reversible counter 3 coincide, the output frequency signal appears at the output of comparator unit 4

which enters the counting input of the second divider 5 and through the first element OR 8 sets in state O counter 2,

When the second divider 5 overflows, the overflow from its output enters through the second element, prohibiting 13 and the second element OR 10 to the input of the second trigger 7 And sets its B unit state, its output Signal through the first element 9 allows the input to the first divider 1 of the reference frequency signals f (, p. The overflow signals from the output of the first divider 1 are fed to the counting input of the reversible counter 3. Changing the code at the outputs of the reversing counter 3 causes a corresponding change in the output frequency. The measurement process The code continues until the second trigger 7 arrives at the counting input through the first prohibition element 12 and the second element OR 10 of the input frequency pulse fg equal in duration to the overflow pulse of the second frequency divider 5.

When the input frequency pulse and the overflow pulse of the second frequency divider 5 arrive at the input of the second trigger 7 from a different sequence, the process of changing the code of the reversible counter 3 occurs in a similar way, while the reversing counter 3 changes from the add mode

the subtraction mode, which sets the first trigger 6. If these pulses arrive simultaneously, then both prohibition elements 12 and 13 are closed and the second element OR 10 does not receive the pulses.

If, on the other hand, the pulses coincide partially, their common part will be prohibited and two impulses, one after the other, arrive at the input of the second trigger 7

the first of which will translate the interp into a single state, and the second will immediately return it to its original state, i.e. the reversible counter code 3 does not change, the multiplier will not fail, and the output frequency f, v will remain unchanged.

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Claims (1)

Formula from b re shadow Frequency multiplier auth. No. 1148088, characterized in that, in order to increase the frequency multiplication accuracy, the first input of the second element AND and another installation input of the first trigger are combined with the first input of the second element OR through the input of the first prohibition element, the output of the second frequency divider is connected to the second input of the second element OR through the entered second element of the ban, while the inputs of the first and second elements of the ban are also connected respectively to the inputs of the ban of the second and first elements of the ban.