SU1427552A1 - Frequency multiplier - Google Patents

Abstract

The invention is related to radio engineering and can be used for frequency multiplication in information reception and transmission equipment and in computer transmission systems. The purpose of the invention is to improve the multiplication accuracy. The frequency multiplier contains two frequency dividers (DF) 1.5, counter 2 reversible counter (PC) 3 ,. block 4 comparisons, triggers 6, elements OR 8, 10, elements AND 9, P. In order to increase the multiplication accuracy, the element AND 12 and the element OR 13 are introduced. Changing the code on the outputs of PC 3 causes a corresponding change in the output. code changes continue until the moment of arrival. On the score, Hbiii input of trigger 7 through the element. OR iO pulse input frequency fef. When a pulse fg and an overflow pulse DC 5 are received at the input g of trigger 7 with a different sequence PC 3, the transition from addition mode to subtraction mode, which sets trigger 6. If the pulses coincide at least, then the coincidence pulse, which enters And 12, through the element OR 13 enters the input of the installation of the trigger 7 and sets it to the initial state, i.e. the PC code does not change and the output frequency remains unchanged. 1. Ш1. About SS with

Description

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The invention relates to radio engineering and can be used for: frequency multiplication in the equipment for receiving and transmitting information and in the transmission systems of computing devices.

The purpose of the invention is to increase the precision of: to-y y shog.

A: Fig. 1 shows the structural electrical circuit of the proposed 5 -1NO5Kitf1 frequency.

The frequency multiplier contains the first frequency divider I, counter 2, reversible counter 3, comparison block 4, second frequency divider 5, the first 6 n second 7 triggers, the first element HJIIi 8, the first element E ,,, the second element OR 10, the second And and the third 12 elements AND and the third element OR 13,

Frequency multiplier works barely ™, in a way that

When the start signal is applied to the second input of the And 11 element, the fax input frequency signal through the AND element And sets the counter 2, the divider 1 and 5 to the initial state, reversible counter 3Pch 3 and through the OR element 13 trigger 7 The reference frequency signal fon goes to the counting input of the counter 2. When the SRI of the output codes of the counter 2 and the reversal counter-3 coincides, the output of the comparison unit 4 appears the output frequency signal f) W) i. which enters the counting input of the frequency divider 5 and through the element OR 8 sets counter 2 into state O. When frequency divider 5 overflows, the overflow pulse from its output comes through the element OR 10 to the input of trigger 7 and sets its B unit state ,, the output signal through the element and 9 permits the arrival at the input of the frequency divider 1 of the signals of the reference frequency G0. The overflow signals from the output of the splitter 1 frequency come from the counting input of the reversible counter 3. Msi-fe some code at the outputs of the reversing counter 3 causes a corresponding change in the output frequency. The process of changing the code continues until the trigger 7 arrives at the counting input through the pulse OR input element 10, often fg.

Upon receipt of both the input frequency and the overflow pulse, de27552 2

The frequency 5 to the input of the trigger 7 in another sequence changes the code of the reverse counter 3 similarly, while the counter 3 moves from the add mode to the subtraction mode, which sets the trigger 6. If these pulses coincide at least partially, then the pulse coincides , an element And 12, through the element OR 13 enters the input of the trigger setup 7 and sets it to its original state, i.e. the code of the reverse counter 3 does not change and the output frequency remains unchanged.

Claims (1)

Invention Formula 20 Frequency multiplier, containing the first OR element sequentially connected and the counter, the bit outputs of which are connected With the corresponding inputs of the first group of inputs of the comparison unit, the first element AND of the first frequency divider and the reversible counter, the bit outputs of which are connected to the corresponding 30 inputs of the second group of inputs of the block. comparison, the second element And, the output of which is connected to the installation input of the second frequency divider, the setting input of the first divider from the frequency, the group of installation inputs of the reversible counter and the first input of the first element OR, the first trigger, the output of which is connected to the control input of the reversible counter, the second element OR, the output of which is connected to the counting input of the second trigger, whose output is connected to the first input of the first element Hj at the same time, the output of the second frequency switch is connected to the second input of the second element .OR or the second installation input of the first trigger, the first input of the second element I is connected to the first input of the second phase ment OR and the first installation the input of the first trigger, their connection point is the signal input of the frequency multiplier, the output of the comparator is connected to the second input of the first element OR and the counting input of the second frequency divider and is the output of the frequency multiplier, the counting input of the counter is connected to the second input of the first element AND, their point so3U27552 unity is the input of the reference clock and the third element OR, the output of which frequency multiplier, and the second is connected to the setup input in the input of the second element And is the second trigger, while the second input the house of the trigger signal of the multiplier of the third element OR is connected to the frequency, which differs in the course of the second element AND so that, in order to ensure accuracy and the second inputs of the third element AND multiplied, entered into it after-connected to the first and 1 connected separately retney element; and the second input of the second element OR.