JPH01288914A - Clock failure detecting circuit - Google Patents

Abstract

PURPOSE:To make smaller the size of a circuit by providing a divider to divide the frequencies of a detected clock into two, a shift register, a coincidence circuit, and an FF, and detecting the clock failure in a fixed time regardless of the failure condition of a clock signal. CONSTITUTION:A divider 1 divides the frequencies of the detected clock into two, and outputs them to a shift register 2. The register 2 inputs the outputs of the divider 1 and the detecting clock, it repeates a count whenever the detecting clock is inputted, shifts the output of the divider 1 stage by stage, and produces the output from the respective block on an m-th stage to a coinci dence circuit 3. The circuit 3 inputs the output of the divider 1 and the respec tive outputs of the (m) pieces in the register 2, and when the all output values are aligned at a certain constant value, the constant level value is outputted by means of the m-th detecting clock. In an FF 4, when the output at the con stant level value and the detecting clock are inputted, the clock failure detecting signal is outputted at the next (m+1)-th detecting clock. That is, since the clock failure can be detected not in the failure condition of the clock signal but in the fixed time, the circuit scale can be made smaller.

Description

[Detailed Description of the Invention] [Summary] Regarding the detection of a clock signal interruption state used in digital communication, the circuit For the purpose of downsizing, in a device that detects clock interruption by comparing the detected clock with a reference detection clock, there is a frequency divider that divides the frequency of the detected clock by two, and a frequency divider that divides the frequency of the detected clock by two, and a an m-stage shift register that inputs an output and a detection clock, repeats counting every time the detection clock is input, and shifts the output of the frequency divider one stage at a time; The output of each m-stage block is inputted to a shift register, and all output values are obtained at the m-th detection clock. A flip-flow knob circuit is provided which outputs a clock loss detection signal when an output of a constant level value and a detection clock are input, and is configured to output a clock loss detection signal at the (m+1)th detection clock.

[Industrial application field]

TECHNICAL FIELD The present invention relates to detection of an interruption state of a clock signal used in digital communications.

Digital processing in information communication equipment is excellent in terms of efficiency and economy, and is widely used.

In devices that process such digital signals, clock signals are used to provide a time reference point and synchronize operations between circuits and devices.

That is, since the clock signal is a basic signal of digital communication, it is required to have high reliability and it is necessary to realize it with a small circuit.

[Conventional technology]

In traditional digital equipment, disconnection of the clock signal
There are two types when considering the 'cutting state'.

That is, there are two cases: a case in which the clock is stopped in a high level' state, and a case in which the clock is stopped in a 'LO-level' state. Clock interruption detection needs to detect both of these states.

In the conventional method, a counter for detecting a ``LOW'' level interruption of the detected clock and a counter for detecting a ``high'' level are each provided in a dual configuration. Even if it occurs, it can be detected.

FIG. 3 is a circuit diagram showing a conventional embodiment.

In the figure, 11 is a first synchronous counter, 12 is a second synchronous counter, 13 to 15 are NOT, and 16 is OR.

17 is FF.

The detected clock is N0 in the first synchronous counter 11.
The second synchronous counter 12 is also directly input to each load input terminal LD via T13. The detection clock is a stable signal that is supplied as long as the power to the crystal oscillator or the like is not cut off, and is input to the terminals CK of the first synchronous counter 11 and the second synchronous counter 12, respectively. Note that the detection clock is
A clock having the same frequency as the detected clock is used.

When the input level of the detected clock input to the first synchronous counter 11 is LOW, the input level of the second synchronous counter 12 is HIGH, and the load value 1011 is loaded.

Now, the first clock of the detected clocks is 'high
Assume that the motor stops at the level h'. The second synchronous counter 12 stops with the load "1011", but the first synchronous counter 11 continues counting up from the next detected clock.

Even in this state, if the detected clock remains stopped, the output of the terminal CO of the first synchronous counter 11 becomes °high' at the "high" level of the detected clock 6 at the 5th count. “LOW” is applied to the terminal EN of the first synchronous counter 11 via N0T14.
The level is input, the counter stops, and the terminal CO becomes “hi”.
maintain the level of gh'.

This 'high' level output is input to the terminal of FF17 via 0R16, and a 'high' level clock disconnection detection signal is input to the terminal when the detected clock 7 of the sixth count is 'high'. Output.

Next, when the detected clock stops at the "LOW" level, the second synchronous counter 12 turns the count-a-knob, and the detected clock reaches the "LOW" level at the fifth count.
' level, the output of the terminal CO of the second synchronous counter 12 maintains LOW', and the FF
17, and when the detected clock 7 at the 6th count is at the LOW' level, L0
Outputs a 1 level clock loss detection signal.

Note that here, the clock disconnection detection time Td is Td = (
N-L+2)

FIG. 4 is a diagram showing timing in a circuit diagram of a conventional embodiment.

The detected clock shown in (8) is input, and the detected clock is "hi" of the first detected clock 1 as shown in (B).
gh", the output of the terminal CO of the first synchronous counter 11 changes from °LO-' to high' at the sixth detected clock 6, as shown in (C), and F
F17 outputs a clock disconnection detection signal which changes to high' at the seventh clock 7.

Conversely, when the detected clock 1 shown in (E) is disconnected at LOW', the output of the terminal co of the second synchronous counter 12 becomes "
At the seventh clock 7, the FF 17 outputs a clock interruption detection signal which changes from "high" to "LOW'" and changes to "LO1".

As described above, conventionally, two synchronous counters with asynchronous load functions are provided in a dual configuration to detect clock interruption.

[Problem to be solved by the invention]] Therefore, in a circuit using a conventional asynchronous counter, it is necessary to have a dual configuration, so when forming a clock disconnection detection circuit in an LSI, the gate size becomes large. A problem arises.

SUMMARY OF THE INVENTION An object of the present invention is to reduce the size of a circuit by detecting a clock interruption at a constant time regardless of the interruption state of a clock signal.

[Means to solve the problem]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

1 is a frequency divider, which divides the frequency of the detected clock by 2; 2 is a shift register, which inputs the output of the frequency divider 1 and the detection clock, and counts each time the detection clock is input. is repeated to shift the output of the frequency divider 1 one stage at a time, and output from each block of m stages. 3 is a matching circuit, which shifts the output of the frequency divider 1 and the m shift registers 2. , and outputs a constant level value when all the output values are equal to a certain constant value at the m-th detection clock.

The flip-flop circuit No. 4 outputs a clock interruption detection signal at the next (m+1)th detection clock when the constant level output of the matching circuit 3 and the detection clock are input.

[For production]

In the present invention, as shown in FIG. 2, in a shift register 2 having m stages, the output of the frequency divider 1 is counted and shifted one stage each time a detection clock is input, and the output from each stage is The respective m outputs are applied to the matching circuit 3.

Therefore, by matching the m outputs of the matching circuit 3, which have a constant value, with the output of the frequency divider 1, it is possible to output a clock interruption detection signal at the (m+1)th detection clock.

〔Example〕

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In the figure, reference numeral 1 is a frequency divider, which is a circuit that inputs the detected clock to a terminal T, divides the frequency by two, and outputs the result from a terminal Q.

Reference numeral 2 denotes a shift register for storing an input clock, and as an example, a shift register consisting of five blocks is shown. divider l
The detected clock counted in is inputted to the terminal S, and the detected clock is inputted to the terminal CK, and the detected clock is sequentially shifted one block at a time each time the detected clock is input.

Further, 3 is a matching circuit, and 01 to 01 of shift register 2
When all the outputs of Q5 are 01 or 0, and the 1 or 0 output of the shift register 2 matches the output from the frequency divider 1, the signal from the register 1 is output. 4 is a flip-flop circuit (hereinafter referred to as FF)
When the output of the matching circuit 3 is 1, a clock interruption detection signal is output from its output terminal Q.

The features of this circuit are as follows: 1. A shift register can be used in place of a watchdog counter.

2. The detection circuit does not change due to the interruption state of the detected clock.

These two points make it easy to create an LSI circuit.

Note that the clock interruption detection time Td is Td - Tf X (m+1) Here, Tf is the detection clock period m is the number of shift register stages It is.

FIG. 2 is a diagram showing an example of the input and output of the shift register 2 and matching circuit 3 of the present invention.

For example, the configuration is such that a disconnection detection signal is output at the detection clock 6 after the detected clock is disconnected.

The detected clock is input to terminal T of frequency divider l and output to terminal 0.
The output is input to the terminal SD of the shift register 2. Note that the shift register 2 operates under the control of the detection clock.

Now, the contents of the shift register 2 when the detected clock does not "interrupt" are as shown in (A), Ql,
The outputs of ports 2.03, Q4, and Q5 alternately appear as "10101" or "01010." The signal denoted SD here is an input signal from the frequency divider l to the shift register 2.

In this state, when the detected clock is turned off, the input to the terminal SD of the shift register 2 is held in a ``high'' or ``LOW'' state, as shown in (B).

Next, after the detected clock is disconnected, when the detection clock of the number of stages of shift register 2 is input (in the case of Fig. 2, the 5th clock), the output of shift register 2 becomes (C) at the first detection clock. The signal shown in (D) is detected by the second detection clock, and the signal shown in (E) is detected by the third detection clock.
), and the signal shown in (F) is output at the fourth detection clock.

Next, at the fifth detection clock shown in (G) manually, Ql, Q2, Q3.04 of all registers
．． The output of 05 is rewritten to “LOW” or “high”.

Here, when the output of the shift register 2 and the output of the frequency divider 1 match in level and are inputted to the matching circuit 3, the matching circuit 3 outputs a signal at a 'high' level. Then, when the next sixth detection clock is input, clock interruption is detected and a clock interruption detection signal is output. This clock disconnection detection signal maintains this state until the supply of the detected clock is restarted.

As described above, by using the shift register 2 and the coincidence circuit 3, a circuit that does not depend on the clock interruption state can be constructed.

〔Effect of the invention〕

As described above, according to the present invention, the clock disconnection detection circuit can be simplified in configuration, so the gate scale of the LSI circuit can be reduced, and as a result, it contributes to improved operating speed and testability.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of inputs and outputs of the shift register 2 and matching circuit 3 of the present invention, and FIG. 3 is a diagram showing an example of a conventional embodiment. FIG. 4 is a diagram showing timing in a circuit diagram of a conventional embodiment. In the figure, 1 is a frequency divider, 2 is a shift register, 3 is a matching circuit, and 4 is an FF. Not shown. Wound r 44 it.

Claims (1)

[Scope of Claims] A device for detecting clock interruption by comparing a detected clock with a reference detection clock, comprising: a frequency divider (1) that divides the frequency of the detected clock by two; and the frequency divider (1). The output of the frequency divider (1
), an m-stage shift register (2) that shifts the output of the block one stage at a time, and inputs the output of the frequency divider (1) and the output of each m-stage block in the shift register (2), a matching circuit (3) that outputs a constant level value when all output values are equal to a certain constant value at the m-th detection clock; and a matching circuit (3) that outputs a constant level value and the detection clock. 1. A clock loss detection circuit comprising: a flip-flop circuit (4) that outputs a clock loss detection signal when the clock loss detection signal is input, and outputs the clock loss detection signal at the (m+1)th detection clock.