JPH0787367B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention is used in a PLL circuit and compares a phase of a divided signal obtained by dividing an external input signal with a reference signal to output a phase comparison signal. It relates to an integrated circuit.

[Prior Art] FIG. 2 is a semiconductor integrated circuit used in a conventional PLL circuit, which compares the phases of a divided signal obtained by dividing an external input signal with a reference signal and outputs a phase comparison signal (hereinafter, referred to as " It is referred to as a "PLL unit".) 10 and FIG. 3 is a system diagram of a receiving portion of the television receiver. As shown in FIG. 3, the PLL circuit 11 forms a closed loop from the voltage controlled oscillator 12, the PLL unit 10 and the low pass filter 13, fixes the phase of the signal output from the voltage controlled oscillator 12, and It is synchronized with the output signal. Further, the PLL unit 10 performs a phase comparison between the frequency-divided signal obtained by dividing the signal obtained from the voltage controlled oscillator 12 and the reference signal at the frequency division ratio instructed by the external device 20 such as a computer, and the phase comparison signal is a low-pass filter. It outputs to 13. In addition, 15 is an antenna, 16 is a mixer, and 17 is an intermediate frequency amplifier.

The PLL unit 10 has six external terminals P1 to P6 as shown in FIG.
have. The comparison signal input terminal P1 is connected to the programmable divider 1, and the enable terminal P2 is connected to the data latch circuit 2.
The data input terminal P3 and the clock input terminal P4 are connected to the shift register 3, and the reference signal input terminal P5 and the phase comparison output terminal P6 are connected to the phase comparator 5.

The shift register 3 sequentially fetches and shifts the 1-bit data signal S3 from the data input terminal P3 in synchronization with the clock signal S4 input from the clock input terminal P4, and stores the predetermined bit data D _t . This data D _t is always output to the data latch circuit 2.

The data latch circuit 2 latches the data D _t and outputs it to the programmable divider 1 in synchronization with the rising (or falling) edge of the enable signal S2 input from the enable terminal P2.

The programmable divider 1 divides the input signal S1 input from the comparison signal input terminal P1 into 1 / n based on the data D _t (value is n) and outputs the divided signal S1 ′ to the phase comparator 4. It is outputting.

The phase comparator 4 detects the phase difference between the reference signal S5 input from the reference signal input terminal P5 and the divided signal S1 'and outputs the phase comparison signal S6 to the phase comparison output terminal P6.

In this way, the PLL unit 10 divides the input signal S1 from the outside into 1 / n based on the data signal S3 and obtains the divided signal S1 ′.
And the phase difference between the reference signal S5 and the phase difference signal S6 are output to the outside.

[Problems to be Solved by the Invention]

The conventional PLL unit 10 is configured as described above, and in order to determine the frequency division ratio n of the programmable divider 1, the three external signals S2 from the external device 20 such as a computer are supplied from the three external terminals P2 to P4. It was necessary to input ~ S4 (hereinafter referred to as "3-terminal input method").

On the other hand, in the recent PLL unit 10, in order to reduce the number of external terminals required for connection with the external device 20 and reduce the cost, the frequency division ratio n is determined by inputting two external signals from two external terminals. There is a demand for a method (hereinafter, referred to as “two-terminal input method”) that can be performed by doing so.

On the other hand, considering the compatibility with the external device 20 that uses the three-terminal input method, there is a problem that it is difficult to easily switch the method for determining the division ratio n from the three-terminal input method to the two-terminal input method.

The present invention has been made to solve the above problems, and a semiconductor integrated circuit used in a PLL circuit which can be compatible with an external device of a new method while maintaining compatibility with an external device of an old method. Aim to get the circuit.

[Means for Solving the Problems]

A semiconductor integrated circuit according to the present invention is used in a PLL circuit, is a semiconductor integrated circuit that compares the phases of a divided signal obtained by dividing an external input signal and a reference signal, and outputs a phase comparison signal. A terminal, a clock input terminal, an enable terminal, a switching input terminal, an external input terminal, an external data signal and a clock signal from the data input terminal and the clock input terminal, and a first enable signal and an internal data signal. A shift register for generating and outputting the signal, the first enable signal, a second enable signal and a switching signal obtained from the enable terminal and the switching input terminal, and in accordance with the switching signal, A switching circuit that outputs one of the first and second enable signals and the internal data signal are output from the switching circuit. Data latch circuit for latching and outputting at the timing of, and the external input signal from the external input terminal, and based on the internal data signal output from the data latch circuit, the external input signal is frequency-divided And a frequency divider that outputs a frequency-divided signal.

[Action]

A switching circuit according to the present invention takes in a first enable signal obtained from a shift register and a second enable signal and a switching signal obtained from an enable terminal and a switching input terminal, and outputs the first enable signal in response to the switching signal. Since one of the second enable signals is output, the first enable signal and the second enable signal can be selected as needed.

〔Example〕

FIG. 1 is a block diagram showing a PLL unit 10 which is an embodiment of the present invention. As shown in the figure, a selector 5 and a switching input terminal P7 are newly provided.

The shift register 3 'similar conventionally takes the data signal S3 and clock signal S4, it outputs the data D _t to the data latch circuit 2, a new enable signal S2' are output to the selector 5. This enable signal S2 ′
Is a signal having the same property as that of the enable signal S2, and as a method of generating the signal, for example, a method of determining whether the signal is active or inactive according to the value of the data signal S3 when the falling edge of the clock signal S4 is detected can be considered. . In this case, the data signal S3 is read when the rising edge of the clock signal S4 is detected.

In addition to the enable signal S2 'described above, the selector 5 takes in the enable signal S2 from the enable terminal P2 and the switching signal S7 from the switching signal input terminal P7. Then, according to the switching signal S7, one of the enable signals S2 and S2 'is selected and output to the data latch circuit 2. Since the other configurations are the same as the conventional ones, the description thereof will be omitted.

In such a configuration, when the switching signal S7 is set so that the selector 5 selects the enable signal S2 obtained from the enable terminal P2, the same three-terminal input method as the conventional method can be used as the method for determining the frequency division ratio n.

On the other hand, when the switching signal S7 is set so that the selector 5 selects the enable signal S2 ', the shift register 3'
The enable signal S2 ′ thus generated is input to the data latch circuit 2. As a result, the data latch circuit 2 latches the data D _t and outputs it to the programmable divider 1 in synchronization with the rising (or falling) edge of the enable signal S2 '. Therefore, the frequency division ratio n of the programmable divider 1 is determined by the two external signals of the data signal S3 and the clock signal S4 input from the data input terminal P3 and the clock input terminal P4.

That is, a two-terminal input method is realized as a method of determining the frequency division ratio n, and there is no need to externally input the enable signal S2 to the enable terminal P2. As a result, the number of external terminals of the PLL unit 10 used for connection with an external device such as a computer necessary for determining the frequency division ratio n of the programmable divider 1 is reduced from “3” in the past to “2”. Equipment and PL
The cost required for connecting the L portion 10 to the external terminal can be reduced.

It is not necessary to connect the switching signal input terminal P7 to an external device because the method of determining the division ratio n can be easily selected by fixing the switching signal S7 to the power supply level or the ground level. The other operations are the same as the conventional ones, and thus the description thereof is omitted.

As described above, since the selection method of the division ratio n can be selected from the three-terminal input method and the two-terminal input method as necessary by setting the switching signal S7, compatibility with the conventional method is maintained. It is possible to support the new method.

〔The invention's effect〕

As described above, according to the present invention, the switching circuit takes in the first enable signal obtained from the shift register, the second enable signal obtained from the enable terminal and the switching input terminal, and the switching signal, and Since one of the first and second enable signals is output according to the switching signal, the first enable signal and the second enable signal can be selected as necessary.

As a result, while maintaining compatibility with external devices of the old method,
The effect is that it can be compatible with external devices of the new method.

[Brief description of drawings]

1 is a block diagram showing a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional semiconductor integrated circuit, and FIG. 3 is a system diagram of a receiving portion of a television receiver. Is. In the figure, 1 is a programmable divider, 2 is a data latch circuit, 3 and 3'are shift registers, 4 is a phase comparator, 5 is a selector, P2 is an enable input terminal, P3 is a data input terminal, P4 is a clock input terminal, P7 is a switching signal input terminal, S2 and S2 'are enable signals, S3 is a data signal, S
4 is a clock signal and S7 is a switching signal. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A semiconductor integrated circuit used in a PLL circuit, which compares the phases of a divided signal obtained by dividing an external input signal with a reference signal and outputs a phase comparison signal, wherein a data input terminal and a clock are provided. Inputting an external data signal and a clock signal from an input terminal, an enable terminal, a switching input terminal, an external input terminal, the data input terminal and the clock input terminal, and generating a first enable signal and an internal data signal. And a first enable signal, a second enable signal and a switching signal obtained from the enable terminal and the switching input terminal, and outputs the first and the first signals according to the switching signal. A switching circuit that outputs one of the two enable signals and the internal data signal at a timing of the output signal of the switching circuit. A data latch circuit for outputting and outputting the external input signal from the external input terminal, and dividing the external input signal based on the internal data signal output from the data latch circuit. A semiconductor integrated circuit having a frequency divider for outputting a signal.