SU1354213A1 - Device for parallel summing of pulse durations - Google Patents

Abstract

This invention relates to automation and computing. The aim of the invention is to increase the accuracy and speed and the expansion of the field of application by determining the arithmetic average of the summable durations. The device contains a switching unit 1, n triggers 5 (where n is the number of information

Description

device inputs), encoder 8, element OR 10, element 11, pulse generator 13 and counter 14. The principle of the device is based on the fact that, depending on the number of signals that are simultaneously located on the information inputs of the device, each The clock pulse in the register (formed by the switching unit 1 and n triggers 5, -5 °). The invention relates to automation and computing and can be used to measure the sum and average duration of the pulses in n channels.

The purpose of the invention is to improve accuracy and speed and expand the scope of application by determining the arithmetic mean of the summable durations, as well as expanding the dynamic range of the summed signals.

Fig. 1 shows a block diagram of a device for the parallel summation of pulse durations; figure 2 - switching unit; on fig.Z and 4 - key and trigger used

in the device.

The device (figure 1) contains the switching unit 1, information inputs 2, -2 devices, outputs 3, -3, the first group of the switching unit} information inputs 4 triggers 5, -5p, outputs 6, -6, triggers, information inputs switching unit, encoder 8, outputs 9, -9 "of the second group of switching unit, element OR 10, element 11, synchronizing inputs of 12 flip-flops, generator of 13 pulses, counter 14, input 15 of the initial installation of the device, installation input 16 of the counter, installation inputs 17 triggers and keys 18.-, (where j is the key number in the group, i is the key group number), each The second of which has information input 19, the first 20 and second 21 outputs, control input 22.

Switching unit 1 can also be performed on 23ji keys having

a parallel shift to the corresponding number of positions proceeds. In this connection, the accumulation of the number of signals present at inputs 2.-2 at a given time actually occurs. With the end of the last interval from the summation group, the readings of the counter 14 and the encoder 8 reflect the result of the summation of the durations. 2 hp f-ly, 4 ill.

the first 24 and second 25 information inputs, output 26 and control input 27 (FIG. 2).

The device operates as follows (FIG. 1).

In the initial state, the counter 14 is reset, trigger 5 is set to one, and triggers are set to c. zero state. This state of the flip-flops 5 is represented by the encoder 8 as zero. In the absence of signals at the information inputs 2, -2j, devices, all keys are 18 blocks

1 switching closed in the lower position (outputs 21) and the information input 4 of any trigger 5 has the potential of its output 6, and the output of the element OR 10 there is a low signal level, therefore coming from the oscillator 13 im. the pulses do not change the state of the flip-flops 5, -5 "and the counter 14. With the appearance of any of the inputs 2, -2 of the input pulse, the keys of the corresponding group switch to the upper position and a single signal from output 6, trigger 5, turns out to be input 42 of trigger 5, output

6 connects to input 4., Output 6, to input 4d, and so on, and output 6, connects to input 4 and a trigger 5 is switched on the front of the pulse received from generator 13 of a clock pulse. and the rest to zero. After (n-1) clock pulses, trigger 5 turns out to be in a single state, and all the others in a zero state. If the input pulse has not yet ended, the unit

313

the signal from output 6, is fed to input 4, as well as through the first key to the element OR 10, its input to the input of element 11 and the front of the counting pulse in the counter 14 is recorded one, and the trigger 5 is set to one. If two input pulses are simultaneously present at inputs 2, -2, then the keys of the two corresponding groups close to the upper position and input 7 is switched; where i 1- (p-2) with output 3j, input 7 - with output 3, and input 7y, with output 3., and for each counting pulse, the unit level at outputs 6, -6, triggers is shifted by two positions, with three input pulses - three positions, and so on, and at the moments of transition of a single signal from the trigger output with a large number to the trigger input with a smaller number, keys 18 ,, -18 ,, and the OR element 10 form a transfer signal, which is detected by the counter 14.

Thus, depending on the number of single input signals that are simultaneously on the device inputs, for each clock pulse in the trigger register, operating on the principle of a ring counter with a unit-position information coding, there is a parallel shift by the corresponding number of positions (bits ), in connection with which the summation (accumulation) of the number of signals present at the input at a given moment of time actually occurs, and with the end of the last interval of the summation group, Sensor 14 and encoder 8 are the code of the sum of the durations of incoming pulses, and in the counter the high bits, and at the output of the decoder the low bits. The same code, but with a comma after the low-order bit of counter 14, will be the code of the arithmetic mean value (relative to the number of information inputs of the device) of pulse durations.

When using switching unit 1 (Fig. 2), the principle of operation of the device does not change.

Fig. 3 shows one of the possible options for the implementation of a key with one information input, two outputs and one control input. (key 18 in figure 1), which is presented

2

g 5

0

g

134

It is an optical waveguide switch consisting of a waveguide 28, control electrodes 29 and 30. And having one optical input 31 and two optical outputs 32 and 33. The electrode 30 is connected to zero potential, at a low potential level on the electrode 29 optical light input 31 enters output 32, and at high output 33.

Figure 4 shows one of the possible implementations of the trigger with dynamic control and optical input 34 and output 35, which contains the first photodetector 36 with S-characteristic, sequentially connected to the first light emitter 37, which is optically coupled to the second photoreceiver. 38 with an S-shaped characteristic connected in series with a second light emitter 39 connected to the output of the inverter 40, the input of which is connected to the primary-1 light emitter 37 and is a control electrical input 41 of the flip-flop.

The trigger works as follows. Suppose that in the initial state the light emitter 39 does not emit, on the bus 41 there is a high potential level, while on the circuit the light emitter 37 is a photoreceiver 36 there is practically no voltage drop. If a light signal arrives at the input 34, it causes an accumulation of charge in the photodetector 36, which reduces its resistance and with a negative voltage jump on the bus 41, the light emitter 37 begins to shine and affects the photodetector 38, and by a positive jump on the bus voltage 41 the light emitter 39 begins to emit, which indicates a record in the trigger unit. If now the photodetector is not affected by light and a zero potential impulse is applied to the bus 41, then the current through the light emitter 37 will not be sufficient to start the emitter, the resistance of the photodetector 38 is high and. light emitter 38 ceases to emit

When using a switching unit 1 operating with an optical information carrier, the element OR 10 (FIG. 1) is an IPD optical circuit with an electrical output and is a combination of optical fibers whose output ends are connected to

one photoreceiver whose electrical output is the output of an OR circuit.

If the keys 18 (Fig. 1) are made in the form of optical switches (light deflectors), then due to the unidirectional property of the light information signal passing through the key information circuit, keys 18, can be excluded from the circuit by connecting the inputs of the OR 10 element directly to the outputs 21 corresponding keys 8gch-1, h because in this case the optical

the signals from the outputs of the 20 keys 18 ,, - 18 are received respectively only at the inputs 19 of the keys 18jf.d-18l. and the output 3J of block 1 and do not arrive at the inputs of the OR 10 element. The latter is necessary for the initial signal to present on the bus connecting outputs 20 to the inputs 19 of the first keys of all groups did not arrive at the inputs of the element OR 10 and did not cause a false transfer signal. To prevent the occurrence of a false transfer signal in electronic circuits, keys 18 ,, -184, n are needed.

Claims (3)

1. A device for parallel summing of pulse durations, comprising a pulse generator connected by an output to a first input of an element AND connected by a second input to an output of an OR element, and an output to a counting input of a counter whose output is an output of the device, characterized in that In order to improve accuracy and speed and expand the scope of application by determining the arithmetic mean of the summable durations, a switching unit, n triggers (where n is the number of information inputs device and the encoder, whose origin is the low-order outputs of the device's summation, and the inputs are connected to the outputs of the respective triggers, each i-th (i 1, n) trigger connected by an information input to the iM output of the first group of outputs of the switching unit, the synchronization input - with the output of the pulse generator, the adjusting input - with the initial input device settings and the installation input of the counter, and the output - with the i-th information input of the switching unit, the control inputs of which are connected to the corresponding information inputs of the device, and the outputs of the second group - to the inputs of the OR element. g 0 tl and h a- switch + 1 2. The device according to Clause 1, which is lacunar with the fact that the block contains n groups of whose, with the first key of each i-th 5 (L 1, p) of the key group is connected to the first output with the i-M output of the second output group of the switching unit, and the information input to the second output of the second and first output 0 (n + 1) -th keys of the same group of keys, and each j-th (j 2, n + 1) key of each i-th group of keys is connected by the first output to the second output of (J + 1) -th key the i-th group, and the second output to the information input of the j-ro key (i + 1) -th group, while the information input of the j-ro key of the first group is connected to the (j-1) -M information input of the unit 0 switching, the second output of the j-ro key of the nth group is connected to the (j-1) -My output of the first group of outputs of the switching unit, and the control inputs of the keys of the i-th group are connected to i-M 5 control input switching unit. 3. The device according to Clause 1, which means that the switching unit contains n groups of n + 1 keys, if than the first key of each i-th (, n) group is connected to the output of the i-th output of the second group of outputs of the switching unit, the first information input is connected to the logical zero bus, and the second 5 information input is connected to the second information input of the second and first information input ( n + 1) keys of the i-th group of keys, with each j-th (j 17p + 1) key of each i-th group connected by the first information input to the second information input (j + 1) -ro of the i-th key groups, .a output - to the first information input of the j-ro key (i + 1) -th group of keys, the first information input j-ro the key of the first group is connected to the (j-l) -M information input of the switching unit, the output of the j-ro key of the n-th group is connected to (j-l) -My output0 five 7135D21: 38 For the first group of outputs of the com-i block, the i-th group is connected to the i-th control mutations, and the control inputs of the keys are connected to the input of the switching unit. 3f Fiz.Z O p CHCH5 37  H FizM Editor H, dumb Compiled by S.Kazinov Tehred L.Olninyk Order 5696/45 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, focKBa, Ж-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Project, 4 dd 9 0 Proofreader M. Sharoshi