SU957437A1 - Optical electronic module - Google Patents

Description

the first photodetector i + 2-th bit and to the opening contact of the second group of switch, the second output of the third photo-receiver i-ro bit is connected to the second output of the fourth photo-receiver i-1-th discharge, to the second output of the fourth photodetector i + 1 bit and to the closing contact of the second group of the switch, the first output of the fourth photodetector i-bit is connected to the base of the transistor, the second output of the third photodetector i + 1-bit is connected to the second output of the fourth photo-receiver i-ro bit, to the second output fourth pho This is the receiver of the i + 2d bit and to the disconnecting contact of the first switch group, and the light source of each bit is connected to the fourth photodetector of the same bit.

Fig, 1 shows the functional diagram of the optoelectronic module; figure 2 - timing diagrams of his work in the mode of information shift.

The optoelectronic module contains in each i-oM discharge the source 1 of light, the transistor 2, the first photodetector 3, the second and the third successively connected photodetectors 4 and 5, respectively, and the first outputs of the photoreceivers are connected to the base of the resistor 2, the collector of which through the source -1 light connected to the power supply bus bar, and the emitter is connected to the common bus, the light source 1 of the previous discharge is connected to the second photodetector 4 of the subsequent discharge, the light source 1 of which is connected to the third photodetector 5 of the previous discharge, the source 1 light of each bit is associated with the first photodetector 3 of the same bit, the output of the generator 7 pulses is connected to the counting input of the trigger 8, equipped with the installation input 9 of the unit state and the reset input 10 at the zero state. the output of which is connected to the switching contact 11 of the switch 12, and the inverse output to the switching switch contact 13, the second output of the second photodetector 4 of the 1st bit is connected to the second output of the first photodetector of the 3rd i-1-second discharge Photodetector 3 i-fl-ro bit size The pin 14 of the switch 12, and the second output of the second photodetector 4 i + 1-th digit is connected to the second output of the first photo-receiver 3 i-ro digit, to the second output of the first photodetector 3 i + 2-th digit and to the opening contact 15 switch 12, the second output of the third photodetector 5 i-ro bit is connected to the second output of the fourth photodetector 16

i-1-th bit, to the second input of the fourth photodetector 16 i + 1-th bit and to the closing contact 17 of the switch 12, the first output of the fourth photodetector 16 i-ro bit is connected to the base of the transistor 2, the second output of the third photodetector 5 i + 1-th digit is connected to the second output of the fourth photodetector 16 i-ro discharge, to the second output of the fourth photodetector 16 i + 1-bit and to the closing contact 18 of the switch 12, the source of light 1 of each discharge is connected to the fourth photodetector is 16 of the same bit.

Figure 2 shows voltage plots Ug (,, -, Ha of the generator output 7 of pulses, and at pin 11 of switch 12 connected to the direct output of flip-flop 8, Uj at pin 13 of switch 12. connected to inverse flip-flop of trigger B and the form of optical signals at the inputs and outputs of the corresponding bits.

Optoelectronic module operates as follows.

When power is supplied to the bus 6, the Optoelectronic module is ready to record information. Counting trigger 8 is set to zero.

In the summing mode, the switch 12 is moved to a position in which contacts 11.14 and 13.15 are closed. In this mode, the light signal to the second photodetector of the i-2 nd bit is supplied continuously. When the first pulse is applied, the counting trigger 8 is transferred to the single state, after which the i-2-th bit goes into the excited state, while the i-1-th bit cannot go into the excited state in the given clock cycle. as its second photodetector 4, through switch 12 is connected to the inverse output of the trigger 8. When the second pulse is applied, the counting trigger 8 is transferred to. the zero state, therefore, at its inverse output there is a high potential, and at the forward output a low one and the recorded unit of information in the previous cycle is entered into the memory of the i-2th digit, and in this cycle it goes into the excited state i -1st bit

Thus, in each subsequent clock cycle, the unit of information is recorded into the previous bit and the next bit is excited.

In the subtractive counter mode, the switch 12 is switched to a position where its contacts 11,17 and 13,18 are closed.

Assume that all the previous bits are i + 3 rd in the excited state. Then, when the first pulse is applied, the countable three ger 8 is transferred to the unit state, i.e. at its first output, a high potential level corresponding to the level of a logical unit. In this cycle, i + 3rd discharge is zeroed, since on the inverse output of trigger 8 a low potential level corresponding to a logic zero level, the leakage current of this discharge is sufficient to reset it. When each subsequent pulse is applied, each previous step is reset. Thus, in these modes, the optoelectronic module operates in units; the initial-normal code, i.e. the number of excited bits in the module corresponds to the weight of the recorded digit. Information display is from light emitters 1 of each bit. In the shift shift, its visualization should be carried out in one bit starting from the second, i.e. in this case, a pair of bits, such as the i-th and i + 1-th, is considered a cell of the module, the external display is taken from the source 1 of the light i + 1-th. bit, which is called the main one, and the i-th bit — additional. In the indicated mode, the number of bit cells is m p / 2, where n is the number of module bits. In the right shift mode, the counting trigger 8 is set to the zero state, the switch 12 is switched to the position at which its pins 11, 14 and 13,15 are closed. The second photodetector 4 i-2-nd time is given a light signal of duration T "ti 2T, where T is the period of the following impulses. When the first pulse is applied, the counting trigger-8 is set to the single state, the additional i-2 th bit goes into the excited state. With the second pulse applied, the counting trigger 8 is set to the zero state, the first photodetector 3 i-2- is triggered. The first bit of information, the unit of information is stored in the memory of the i-bit bit, besides, in this cycle, the second photodetector 4 of the main i-1-th bit is triggered and the excitation is given. ny Thus, in two clocks, a unit of information is written into the unit's bit cell. When the third pulse is applied, the trigger is set to one state, the second photodetector 4 of the additional i-ro bit is triggered, and a single bit of information is excited by the i-ro bit, the i-bit bit is reset. (the light signal of the second photodetector of the 4th i-2nd of the discharge during the third cycle and in the subsequent cycles is no longer given). With the supply of the fourth pulse, the counting trigger 8 is set to the zero state, goes into the excited state of the main i + 1-th bit, the information unit recorded in the previous cycle is entered into the memory of the i-ro bit, zero i-1 -th bit. Consequently, in two cycles there was a shift to the right in the module of the recorded unit of information by one bit cell. A further shift to the right in the module of the recorded unit of information occurs in a similar way, i.e., with the arrival of every two pulses, the shift is performed by one bit cell. In the left-shift mode, the information units in the optoelectronic module switch 12 is switched to a position in which the contacts 11,17 and 13,18 are closed. In the left-shift mode, a pair of bits i + 1st, i-th is considered the bit cell of the module, and the external indication is taken from the light source 1 of the i-th bit, starting from the last, and i + 1-th bit , i-th - the main. Suppose that i + 3rd and i + 2nd bits are in the excited state. When the first pulse is applied, the counting trigger 8 is set to the one state, the auxiliary j + 1st bit goes into the excited state, and the i + 3th bit is zeroed. With the supply of the second pulse, the counting trigger 8 is set to the zero state, the main i-utt bit is transferred to the excited state, a unit of information is stored in the i + 1 bit memory, i + 2 bit is zeroed . Thus, in two clocks1, the left unit of information is shifted by one digit cell in the module. A further shift to the left in the module of the recorded unit of information occurs in a similar way, i.e. with the arrival of every two pulses, the shift is accomplished by one bit cell. In the mode of recording and shifting any information, the switch 12 is set to a position in which the contacts 11, 14 and 13, 15 are closed. In this mode, any information can be written to the module sequentially and shifted. In the recording and right shift mode, any information needs to be visualized after one bit, starting from the second. A couple of bits, for example, the i-th and i + 1-st, are considered the bit cell of the module, with the external

Katsi is taken from the source 1 of the light of the i-ro discharge, and the i + 1st discharge is considered auxiliary, the i-th main.

We write, for example, the code IT. For which, the counting trigger is set to the zero state. A light signal is applied to the second photodetector 4 of the auxiliary i-2d bit. When the first pulse is applied, the counting trigger 8 is set to the one state, the i-2-th bit goes into the excited state. With the supply of the second pulse, the counting trigger 8 is set to the zero state, the main i-1-bit goes into the excited state, and a unit of information is stored in the memory of the i-2-th bit. When applying the next four pulses in the same way, the 1st and i + 1st, i + 2nd and i + 3rd bits are excited. Moreover, with the arrival of the fifth pulse, the light signal is no longer sent to the second photodetector of the 4th-i-2th bit, this bit is zeroed, and when the sixth pulse is fed, the i-2i-1 i + 1 i + bits 2

i-1st bit. Thus, information 0110 is recorded in the module.

The information recorded in the module can be shifted to any number of bit cells. To shift right

or to the left by p bits, it is necessary to apply to the counting input of the trigger 2 n input pulses.

For our example, to shift the right of the recorded information IT to

one bit cell needs to give two pulses. When the seventh pulse is applied, the counting trigger 8 is set to the one state, i + 4th bit is triggered, one

information is entered into the i + 3 rd bit of memory, the i-th bit is zeroed, since, at the inverse output of the counting trigger 8, there is a low level of potential.

With the supply of the eighth pulse, the counting trigger 8 is set to the zero state, the i + 5th bit is raised, the unit of information is entered into the i + 4th bit memory,

zero i + 1 bit.

Table 1 shows the process of shifting the recorded information.

Table 1 i + 3 i + 4 i + 5

00 1 O O

O00 But since the information output is each i-th, starting with the last one, the bit, the shifted UN code will be. Thus, to record the code, it is necessary to send a light signal to the second photodetector 4 within 2 (n-1 cycles, where n is the number of unit bits, and on the next two cycles this light signal should be absent. For 1D, PI of code J 1 ... 11. J3 1 1 .. .1 1, R nk-1 light signal to the second photodetector 4 i-2 of the bit, it is necessary to apply 3 for 2 (nk-1) cycles, during two cycles, interrupt its supply, and then again give a light signal for 2k cycles. Moreover (k bits + (n-kj bits n and bits), where n is the number of bits in the module. left shift switch 12 is shifted to a position where its contacts 11,17 and 13,18 are closed. The left shift process is carried out in the same way. When writing information in parallel, the module switch 12 is set to the same position as BtipaBo shift mode, and the counting the trigger 8 is set to one state, and with the supply of a positive potential to the corresponding bases of the transistors, the corresponding additional bits of the module transfer to the excited state. When the second pulse is applied, the trigger 8 goes to the zero state, a unit of information is entered into the memory of the corresponding main bits. Thus, memorization and indication of the recorded information in the bit cell of the module occurs in two cycles.

Consider the shift of any recorded information in the module. Let code 11010 be written in the module, it must be shifted to the right. Shifting information by one bit cell occurs in two clocks, i.e. there is a push-pull shift register, which functions with the correct manner. During the first shift cycle, the counting trigger 8 is established in the unit state and a high potential level is present at the second terminals of the photoreceivers. 4 of all additional bits and the photo receivers 3 of all the main bits of the cells of the module. Since the photodetector 4 i-2-. of the additional bit does not have a light signal, it is nullified, a unit of information is entered in the i-1-bit bit by positive feedback between the photodetector 3 and the light source 1 of this bit, and the i + 2 nd bit The switch goes into the excited state, since a high potential level is present on the photodetector 4 of this bit and the light signal of the source 1 of the main i + 1-bit light / i + 3-th bit is not excited, since its photodetector 4 at the same time there is no high potential and light signal , i + 4th bit is zeroed out, a unit of information is stored in the i + 5th bit memory, i + b-th bit is excited, because Discharge cells I-2, i -1 if. i + 2, i + 3 Recorded. code in bits: for the first clock for the second clock for the third for the fourth for the fifth clock

there is a high potential level and a light signal coming from the output of the i-t-5th bit, and the i-t-7th bit remains in a non-excited state.

During the second shift stroke, the trigger 8 is set to the zero state and a high potential level is present at the second terminals of the photodetectors 3 of all additional

0 bits and fotopronems 4 of all main bits of the bit cells of the module. Due to the fact that there is no light signal on the photodetector 4 of the i-1 st bit, this bit

5 is zeroed out, the unit of information is stored in the i-ro memory and i + 2-nd bit, i + 1-th bit remains in the excited state, since its photodetector 4 simultaneously has a high potential level and light signal from i-ro discharge source 1 light, i + 3-n discharge goes into excited state, because its photodetector 4 simultaneously has a high potential level and light signal from light source i + 2 nd discharge Yes. It remains in the unexcited state i + 4th bit and zeroes i + 5th bit, since there is no light signal on its photodetector 4, on the second one there is no light signal. The water of the photodetector 3 has a low potential, a unit of information is stored in the memory of the i + 6th bit, the i + 7th bit is excited,

5 since the second output of the photodetector 4 has a high potential and a light signal from the source 1 of the light i + 6th bit.

Table 2 shows the shift in the discharge cells in follow steps, performed in a similar way.

Claims (2)

Table 2 110 11 1 11 11 0111 0011 0001 l + 4, i + 5 i + (), i + 7 1100 0110 o 01 1 100 1 1100 1110 To shift the recorded information to the left, the switch 12 is shifted to the position where its contact 11,17 and 13,18 are closed. The process of shifting to the left is similar. The operation of the optoelectronic module in the switch mode is similar to the operation of the module in the right shift mode, the recorded information (FIG. 2). The information outputs of the module are each optical output of the main bit of the discharge cell. Moreover, the commutation mode is carried out when each two input pulses are fed. The optoelectronic module can be used in automation and computing devices as reversible counters and shift registers, a dynamic display board, an optoelectronic switch of the time interval converter into the code, and a sequential equalizer. The invention includes an optoelectronic module containing in each i-oM discharge a light source, a transistor, a first photoreceiver, a SECOND and a third photodetector in series, the first terminals of which are connected to the base of the transistor, the collector of which is connected to the power supply bus, and the emitter is connected to a common bus, the previous discharge light source is connected to the second photodetector of the next discharge, the light source of which is connected to the third photoreceiver of the previous discharge, the light source of each discharge Associated with the first photodetector of the same discharge, characterized in that, with the aim of expanding the functionality and increasing the reliability of its operation, a counting trigger, a switch and a fourth photodetector, nickname, are inserted into it. And the output of the pulse generator is connected with the counting trigger input, the direct output of which is connected to the switching contact of the first switch group, and the inverse to the switching contact of the second switch group, the second output of the second photodetector i-ro bit is connected to the second the output of the first photodetector of the i-1-th digit, to the second output of the first photodetector i + 1-th digit and to the disconnecting contact of the first switch group, the second output of the second photodetector i + 1-th digit is connected to the second output of the first photodetector i- ro of the discharge, to the second output of the first photodetector i + 2 nd discharge and to the disconnecting contact of the second group of the switch, the second output of the third photoreceiver of the i-ro discharge is connected to the second output of the fourth photoreceiver of the i-1st discharge, to the second output fourth photodetector i + 1-th bit d a and to the closing contact of the second group of the switch, the first output of the fourth photodetector i-ro bit is connected to the base of the transistor, the second output of the third photodetector i + 1-bit is connected to the second output of the fourth photodetector i-ro bit, to the second output of the fourth photodetector i + 2d bit, to the closing contact, the first group of switches, and the light source of each bit is connected to the fourth photodetector of the same bit. Sources of information taken into account in the examination 1. Japanese Patent I 48-43470, cl. H t) 3 K 23/14, 1973. 2. USSR author's certificate for application number 2739229 / 18-21, cl. H 03 K 23/12, 1979. ff / n / (fff