SU1348991A1 - Pulse train to square pulse converter - Google Patents

Abstract

The invention can be used in pulse signal processing systems and allows improving the noise immunity of the device. The converter contains 1 clock pulse generator, AND 2 and 3 elements, RS flip-flop 5, block 7 task setting codes, 8 imluses counter, 2И-OR 10.1-10.К elements and delay element 12. To achieve this goal, the RS flip-flop 6, the AND 9.11 and 17 elements, the inverter 15, the pulse counter 16 are entered into the device, and new functional connections are formed. 2 Il. With with 4 00 x QD

Description

The invention relates to a pulsed technique and can be used in pulsed furna processing systems. ioH.

The purpose of the invention is to increase the (:;);

FIG. 1 is an electrical functional diagram of the device in FIG. 2 - time diagrams that show his work.

The converter of a series of pulses into a direct pulse contains a generator of 1 clock pulses, the output of which is connected to the first inputs of the first 2 and second 3 elements AND, ijTopot i the input of the elements 3 and connected to the output bus 4 and the direct output iiejiBoro RS-TjJiir repa 5, the third input - with the inverse output of the second short-circuit trigger 6 and the first input of the block 7 specifies the pause, and the output - with the counting input of the first counter 8 pulses, the R-input of which is connected to the S-output of the RS-trigger 5 and the third element I 9, pr m1 1e outputs - with matching first inputs K ele 2I-OR 10. 1-10.K event, and inverse outputs - with corresponding second inputs K of elements 2I-OR 10. 1-10.K, tert1 and the fourth inputs of which are connected to: the corresponding outputs of the pause setting unit 7, and vpocy - with the corresponding inputs of the fourth element And 11, the output of which through the delay element 12 is connected to the R input of the trigger 5, the second input bus 13 is connected to the second input of the pause setting unit 7, the first input bus 14 is connected to the second IEE / 1OM element And 2, the first input of the element And 9 and through the inverter 15 with K pD11m RS-flip-flop 6 and the R-input of the second the counter 16, the counting input is connected to the output of the element 2, and the outputs to the corresponding inputs of the fifth element 17, the output of which is connected to the 3 input of the RS flip-flop 6, the direct output of which is connected to the second input of the element 9.

The pulse train to square pulse converter works as follows: 1M image.

In the initial state, the RS-triggers 6 11 5 and the counter 16 pulses are reset.

Before starting work, the input iiiHHy 13 is given a signal in the form of a parallel binary code that specifies the maximum duration of the pause between bursts of the series (a shift register can be used, for example, as a pause setting block).

Upon arrival on the input bus 14 of the first pulse of the series (Fig. 2a), the element And 2 opens and the pulses with

Q clock pulse generator 1 is fed to the counting input of the counter 16 pulses (Fig. 2b). The minimum duration of the input pulse series is set by connecting certain

5 outputs of the counter 16 pulses to the inputs of the element And 17. If the duration of the input pulse of a series is less than the minimum specified (for example, when a short-pulse interference occurs),

0 then the signal through AND element 17 does not pass, and the pulse counter 16 is zeroed by high potential from the output of the inverter 15 after the end of the input pulse. If the activity

The 5 input pulse of the series is larger than the minimum set value, then the signal from the output of the And f7 element sets the triggers 6 and 5 (through the And 7 element) to one state, and the signal from the output of the And 9 element simultaneously zeroes the counter of 8 pulses (Fig. 2c) . At the end of the input pulse, trigger bis output of trigger 5 is reset to bus 4, a high potential is transmitted, i.e. the formation of a rectangular output pulse begins (Fig. 2d).

At the same time, iio, at the end of the input pulse, opens the element I 3 and the pulses from the generator 1 of clock pulses arrive at the counting input of the counter 8 pulses (Fig. 2e). The pause code received from block 7 of the pause task is supplied to the corresponding inputs of the K elements 2I-1SH10.1-10.K. If the pause between pulses is not more than the specified one, then the formation of a rectangular output pulse continues for a series of input pulses (Fig. 2e). If the duration of the pause between pulses is greater than the specified one, then one (or several) 2I-OR 10 elements are triggered, AND 11 is opened, and the signal through delay element 12 zeroes the trigger 5 (the number of 2I-OR 10 elements is determined by the specified pause code). Formation process

0

five

0

five

0

the rectangular output pulse is terminated.

Claims (1)

Invention Formula The pulse train transducer into a rectangular pulse containing the first input bus, the first RS flip-flop, whose R-input is connected to the output of the delay element, and the direct output to the output bus and the first input of the first element And, the second input of which is connected to output of the clock generator, and the output with the counting input of the first pulse counter, the direct outputs of which are connected to the first inputs of the corresponding K elements 2I-1ShI, inverse outputs - with the second inputs of the corresponding K elements 2I-IPR1, the third and fourth inputs which are connected to respective outputs pause specifying unit, and outputs - to the corresponding inputs of the second AND gate, whose output is connected to an input of a delay element, a second a o 6 o I G Editor L.Pcholiiska Compiled by S. Ermakov Tehred L. Oliynyk Order 5199/56 Circulation 899 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 an input bus connected to the first input of the pause setting unit, characterized in that, in order to improve noise immunity, a second pulse counter, a second RS flip-flop, a third, fourth and fifth elements and an inverter whose output is connected to R- are additionally introduced the input of the second RS flip-flop and the R-input of the second counter, and the input with the first input bus and the first inputs of the third and fourth And elements, the output of the last of which connected to the R input of the first pulse counter, and the second input to the direct output of the second trigger, the inverse output of which is connected to the second input of the pause task unit, and the S input to the output of the fifth And element whose inputs are connected to the corresponding outputs of the second pulse counter, the counting input of which is connected to the output of the third And, the second input of which is connected to the output of the generator of clock pulses. Proofreader S. Shekmar