SU1298875A1 - Clock synchronization device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention is improving noise immunity - achieved by using digital filtering of short noise. To achieve this goal, an OR 4 element is entered into the device. The device also contains D-type triggers 1 and 2, an inverter 3, a matching element 5, a clock bus 6, an output bus 7, and a control bus 8. The impact on the device of interfering signals with a duration greater than the duration of the clock pulses is unlikely, since in each case, the variation of the duration of the generated clock pulses is possible. 2 Il. 2 O 5 L with Z 1. in s. GchE oo OS --3 O1

Description

FIG ..

The invention relates to a pulse technique and can be used in automation and computing devices.

The purpose of the invention is to improve the noise immunity by using digital filtering of short noises.

Figure 1 shows an electrical functional diagram of the device; 2 shows timing diagrams for his work.

The clock synchronization device contains the first 1 and second 2 triggers of the D-type, inverter 3, the element OR 4, the element 5 of the match. Moreover, the direct output of the first trigger 1 is connected to the D input of the second trigger 2, the C input of which through the inverter 3 is connected to the bus 6 clock pulses connected to the first input of the coincidence element 5 whose output is connected to the output bus 7 and C - the input of the first trigger 1. The R-input of which is connected to the S-input of the second trigger 2 and to the output of the OR element, the first input of which is connected to the bus 6 clock pulses, the second to the bus 8 control and to the D input of the first trigger 1 .

The device works as follows

In the initial state on bus 8 there is no signal. The trigger 2 finds c in the single state, and at its inverse output a low voltage level (fig 2d), therefore element 5 is closed at the first input and there is no signal on the grgun 7 (fig 2h). Trigger 1 cleared.

By establishing a high voltage level on bus 8 (FIG. 2b) by dropping the clock (FIG. 2b), trigger 2 is set to a state where the voltage is high at the inverse output, as at the D input of the trigger. On the leading edge of the next sync pulse (Fig. 2a), trigger I is set to one, since its D input has a high level of control signal, and at the same time this pulse is generated on bus 7 of the device. By dropping this clock pulse, trigger 2 is shifted to one state and element 5 closes at the first

five

0

the input that prohibits the passage of sync pulses to the C input of the trigger,

When the control signal is removed, the trigger 2 is maintained in a single state by pulses from the output of element 4, and when the control signal is removed, at the time of generating the clock pulse, i.e. the action of the sync pulse, element 4 prohibits the transfer of the flip-flops 2 and and the distortion of the output pulse of the device (FIG. 2d),

When a device is interfered with by a control bus with a duration shorter than the duration of a clock pulse, the device does not generate a clock pulse at the output, since after the effect of the interfering signal has passed, the triggers 2 and 1 are reset (Fig. 2c).

The device is guaranteed to receive a clock pulse when the duration of the control signal

t 7t -7

 H S v- c.ts U

where T is the period of the following clock pulses;

 - the duration of the sync pulse.

Operation uncertainty zone

devices are defined as follows

inequality:

, 2T, -g, which is associated with the discrete operation of digital devices and the uncertainty of the instant of the onset of the control signal.

However, the impact on the device interference signals duration,. a longer duration of the sync pulses is unlikely, since in each particular case there is a large variation in the duration of the sync pulses.

Claims (1)

Invention Formula A clock synchronization device containing two triggers, each of which is D-type, the direct output of the first of which is connected to the D input of the second trigger, whose C input through the inverter is connected to the clock bus, which is connected to the first input of the coincidence element, connected to the output bus, the control bus, which is different from the fact that, in order to increase noise immunity, an OR element is entered into it, the lead input of which is connected to the clock pulse, the second one is connected to the D input of the first trigger. and the control bus , Exit - with R-BXOReditor V. Petrash Compiled by T. Sokolov Tehred A. Kravchuk Proofreader A.T. Order 896/57. Circulation 902 Subscription VNIISH State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 the house of the first trigger and with the S input of the second trigger, the inverse output of which is connected to the second, the input of the coincidence element, the output of which is connected to the C input of the first trigger.