SU1307531A1 - Frequency multiplier - Google Patents

Abstract

FIELD OF THE INVENTION The invention relates to radio engineering and provides increased stability of the coefficient. multiply. The input periodic signal is converted by the pulse shaper 1 into narrow pulses, which zero the sawtooth generator 2 and discharge capacitor 3 through the switch 5. The memory 6 amplitude value of the saw voltage is stored in memory unit 6 f. The voltage divider 7 sets the coefficient. multiply frequency. At the moment of equality of the voltages at the inputs of the comparator 4, according to the signal from its output, the keys 5.8 open. The selection of the parameters of the device blocks should be such that in the closed state the residual voltage drop on key 8 would be somewhat greater than on key 5. As soon as during subgauge of capacitor 3, the voltage drop on key 5 becomes less than on key 8, the status of comparator 4 changes and the keys 5.8 are closed. Stability the multiplication is increased by inserting the key 8. 2 Il. from € (L

Description

The invention relates to radio engineering and can be used for frequency multiplication, in particular in devices for controlling phase shift,

The purpose of the invention is to increase the stability of the multiplication factor,

Figure 1 shows the structural electrical circuit of the proposed frequency multiplier; figure 2 - timing charts of his work,

The frequency multiplier includes a pulse former 1, a sawtooth voltage generator 2, a capacitor 3, a comparator 4, a first switch 5, a memory block 6, a voltage divider 7 and a second switch 8.

The frequency multiplier works in the following manner.

The input periodic signal is converted by the pulse shaper 1 into narrow pulses, which nullify the oscillator generator.2 of the saw voltage and discharges capacitor 3 through the switch 5. At the end of the pulse of the shaper 1, the voltage of the saw saw voltage 2 rises linearly. Its range is determined by the input signal period of the pulse builder 1. In memory block 6, the amplitude value of the sawtooth voltage is stored. Voltage divider 7 determines the frequency multiplication factor. At the time when the sawtooth voltage at the first input of the comparator 4 (FIG. 2a, curve 1) is equal to the reference voltage (FIG. 2 and curve 2), at its second input, the comparator 4 generates a voltage drop (FIG. 2 ) at the exit. This signal opens the keys 5 and 8. At the same time, the discharge time of the installation capacitance C through the key 8 will be less than the charging time by the same voltage value uV of the capacitor 3, since the value of the capacitor of the capacitor 3. Thus, during charging of the capacitor 3, the potential of the first input of Gfg.2 a curve) of the comparator 4 will be maintained above the potential of its second input (Fig. 2a of the curve 2), which ensures a stable closed state of the keys 5 and 8. Pe termination of transient processes the magnitude of residual stresses on

five

0 5 About 5 0 5

keys 5 and 8 will be defined as the value of them; the resistances in the open state, and led them through them. Moreover, the parameters of the unit 7 voltage, capacitor 3,. the voltage rise rates of the generator 2, the choice of the elemental base or the structure of the keys 5 and 8 must be determined so that in the closed part the residual voltage drop on the key 8 would be somewhat greater than on the key 5. As soon as during the charging of capacitor 3, the voltage drop on key 5 becomes less than on key 8, the potential of the control voltage from the output of comparator 4 changes (Fig. 2b), keys 5 and 8 will close. At the first input of the comparator 4, the linearly increasing voltage will begin to form again, and at the second input it will jumpwise set the reference voltage from the voltage divider 7, which ensures the second stable state of the keys 5 and 8 (open). Then the process is repeated once again, where n is the multiplier of the frequency multiplier.

Claims (1)

Formula of Invention A frequency multiplier comprising a serially connected pulse generator, a sawtooth generator, a capacitor and a comparator, a serially connected memory block, whose input is connected to the output of the sawtooth generator, and a voltage divider whose code is connected to the second input of the comparator, the first key, which is connected between the point of connection of the capacitor with the comparator and the common terminal, while the first and second control inputs of the first key are connected respectively with the output to form n pulses and a output of the comparator, characterized in that, in order to increase the stability of the multiplication factor, it entered the second key, the input and output of which are respectively connected to the output voltage divider and to the common bus, and a control input - with the output of the comparator. 2