SU1401552A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering. The aim of the invention is to expand the range of synthesized frequencies. In order to achieve the goal, the series-connected power source 14, the voltage source 20, the synchronous filter (SF) 6, the charge unit 12 (53) and the storage capacitor (NC) 10, connected in series 19, are injected into the device. D), C) K 18 non-current poitoritos. icii, differential y-1. 21. flip-flop 22 and block 23 control 111, as well as SF 7, 53 13, NK 11, thread source 17, b. Yuki 15 and 16 bit, TsA11 9 and e,: 1st OR OR 24. The maximum synthesized frequency of the input pulses /, iiKi 1/2 / ,, iii Minima. The frequency is determined by the maximum allowable value of the interval in ) eme1 {and l, if we neglect the value of the time interval / | / „„, 1- It is limited by nonconclusions,: the 1 st constant time of the discharge of the NC I) and 11 due to the finite value of co. The electrical resistances of the transistors are in the locked state and the final input resistances of the source repeater unit 18. Taking into account the values of leakage resistance mippim. the frequency can be 1 l several tens of hertz and. next; 1no, the device provides a significant coefficient. uncovered by dianazone. 1 h. the item of f-ly, 2 nl. (Oh (L

Description

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The invention relates to radio engineering and can be used to build digital receivers and transmitters, controlled function generators, converters of digital values into frequency, voltage, current.

The aim of the invention is to expand the range of synthesized frequencies.

FIG. 1 shows a structural electrical circuit of a digital frequency synthesizer; in fig. 2 shows an example implementation of a control unit.

The digital frequency synthesizer contains the oscillator 1 of the reference frequency, the first register 2 of the frequency code, the second register 3 of the frequency code, the first counter 4 with a variable conversion factor, the second counter 5 with a variable conversion factor, the first synchronous filter 6, the second synchronous filter 7, the first a digital-to-analog converter (D / A) 8, a second DAC 9, a first storage capacitor 10, a second storage capacitor 11, a first charging unit 12, a second charging unit 13, a first power supply 14, a first block 15, the second block 16, second power supply 17, source repeater unit 18, current carrying element 19, reference voltage source 20, differential amplifier 21, trigger 22, control unit 23, OR element 24. In this case, control unit 23 contains the first element HE 25, the first element I 26, the second element And 27, the third element And 28, the fourth element. And 29, the second element is NOT 30, the first element is 31 delay, the second element is 32 delay, element OR 33.

Digital frequency synthesizer works as follows.

The frequency conversion factor is defined by two codewords. The number n is entered in the first register 2, and the number m in the second register 3, the outputs of which affect the corresponding bits of the first 4 and second 5 counters, giving them conversion factors in the range from 1 to 1 and 1 to m, respectively.

The output pulses of the oscillator 1 with the frequency / o appear at the output of the first counter 4 with the frequency fn / n. In addition, the input number p is converted by the first D / A converter 8 into a proportional voltage, which creates a regulating voltage at the information inputs of the first charge unit 12 and the first discharge unit 15. A regulating voltage proportional to the number t is created at the output of the second DAC 9 and is fed to the information inputs of the second charge unit 13 and the second discharge unit 16. The pulse from the output of the element OR 24 for a time equal to the pulse duration of the generator 1 is fed to the first control input of the first charge unit 12 and through it the charge of the first 10 and second 11 storage capacitors starts in the interval

0

time t. The first 12 and second 13 charge units can be made in the form of, for example, (not shown) two transistors, the emitters of which are combined, and a current generator is connected to them, which is connected via a switch to the first power source 14. The first and second outputs of the first 12 and second 13 charging units are the collectors of the first and second transistors, with

In this case, the transistor modes are selected so that the collector currents of the first and second transistors are different. Therefore, at the beginning of the time interval / i on the first 10 and second 11 storage capacitors there is a potential difference, which

5 enters through the source repeater unit 18 to the inputs of the differential amplifier 21. The voltage difference at its inputs sets the trigger 22 to one state. Due to this, in the control unit 23, using the first delay element 31 and the second element 27 on the first output of the control unit 23, a positive pulse of duration t is formed. After its termination, the supply of the permitting voltage to the first control input of the first charge unit 12 ceases and the permitting voltage appears on the first control input of the second block of the 16th digit due to the arrival of two positive levels at the input of the first element I 26 and the formation pulse at the fourth output of control unit 23. The first 15 and second 16 blocks of the discharge are made similarly to the first 12 and second 13 blocks of charge. As a result, the first 10 and second 11 storage capacitors are discharged, and the first storage capacitor 5 is discharged with a large current. After the time interval / a, the voltage on the first storage capacitor 10 will become less than on the second storage capacitor 11, as a result of which the polarity will change

0, the voltage at the input of the source repeater unit 18 and the trigger 22 switches to the zero state. The voltage drop from the second output of the trigger 22 is converted in the control unit 23 into a pulse of duration t, which is generated by

5 of the third element And 28, and the second delay element 30, and supplied to the second output of the control unit 23. This pulse arrives at the first control input of the first block of the 15th digit. In this case, the first storage capacitor 10 is discharged by a large current in the interval t than the second storage capacitor 11. The potential difference created through the unit 18 of the source repeaters goes to the inputs of the differential amplifier 21 and maintains the trigger 22 in the zero state. After a time interval t, the permissive voltage at the first control input of the first discharge unit 15 is turned off and a pulse arrives at the first control input of the second charge unit 13 at the fourth output of the control unit 23. Since the information input of the second charging unit 13 is supplied with voltage from the output of the second DAC 9, the first storage capacitor 10 is charged with a higher current than the second storage capacitor 11. After time / 2, a moment occurs when the voltage on the first storage capacitor 10 exceeds the voltage the second storage capacitor 11. At this point, the trigger 22 is switched. In this case, the pulse at the fourth output of the control unit is turned off, and by a positive voltage drop

ten

potentials are approximately equal. As a result, the frequency of the pulses of the output frequency synthesizer is used as the fifth output of the block.

nor, is equal to /, / o-

The charge and discharge of the first 10 and storage capacitors n relative to the average level L U time interval t after a pulse from the first counter 4 an additional capacitor 10 charge the first source 14 power supply 12 charge less current

on a single trigger output 22 form-5 storage capacitor 1

current. Therefore, at the end of the interval t, the first cumulative cond turns out to be charged to the side of the strand than the second accumulate the capacitor 11. On the first interval

The voltage at the first output of the control rod 23 is controlled and the cycle of operation is repeated.

The number of cycles t and / 2 stacked in the period of arrival of pulses

from the first counter 4, the first 20/2 accumulator is determined. The accumulator capacitor 10 is recalculated from the second counter 5. The second block is discharged by the second block 16, discharge ;;

which is controlled from the output of the third element AND 28 of the control unit 23 large

current. Therefore, at the end of the time interval t, the first storage capacitor 10 is charged before a high voltage than the second storage capacitor 11. In the | first time interval

In order to output the pulse of the first counter 4, the second counter 5 is set to zero, the number of switchings of the trigger 22

current than the second cumulative condenser through the OR element 33 of the control unit 23 control 25 —thor 11. The end of the time interval ti corresponds to the counting input of the second counter 5. If between the two output pulses of the first counter 4 the input of the second counter 5 receives less than m pulses, then at start the second synchronous

It corresponds to the point in time when the potential on the first storage capacitor 10 becomes less than the potential on the second storage capacitor I. After this point in time, the second inter filter 7 begins, which coincides with the switching 30 of the time t, which, unlike the first counter 4, enters the second the synchronous filter 7 from the second counter 5 receives a positive level, which exceeds the level at the output of the first counter 4 at the time of gating. Difference

time interval t, the first storage capacitor 10 is discharged by the current of the first block 5 discharge and a larger value than the discharge current of the second storage capacitor 11. At the end of the second interval

The levels are memorized by the second synchronous35 of time t, the first cumulative condenser 7, and is used for the regulator 10, is discharged to obtain a value of a charging potential and discharge of a lower potential than the second accumulating 10 and second 11 cumulative condenser 11. At through the second charge unit 13 from the time interval tz, the first accumulator of the convoy power source 14 and through the second-sensor 10 is charged from the second unit 13

block 16 bit from the second source 17 charge faster than the second cumulative

nutrition An increase in current leads to a diminished capacitor 11, after which the second block 13

charge time and, therefore, the charge is turned off and the first

to an increase in the number of pulses, by charge unit 12 and the next begins

stepping on the second counter 5 for the period of operation of the device. The duration of the inverse of the pulses of the first counter 5. If .g of intervals of time i is constant and is set

the number of such pulses is greater, then the pulse duration at the first and third gates of the second synchronous filter 7 remembers the negative voltage difference at its inputs, which leads to a decrease in the current of the second block 13

The outputs of the control unit 23 (the delays of the first 31 and second 32 delay elements), and the duration of the inte1) time / 2 shaft are determined by the ratio of the values

charge and second block 16 bit and to reduce 50 currents at the outputs of the second block 16 bit

the number of pulses in the second counter 5. In connection with the fact that the second synchronous filter 7 has a longer time constant compared with the gating period, at its output such

for the first time interval i- and the magnitude of the currents at the outputs of the second charge unit 13 for the second time interval t-i.

To balance the values of charge and discharge currents of the first 10 and second 1

the output voltage at which at the time of the storage capacitors in the period sometimes the counter 7 receives exactly m pulses of the pulses of the first counter 4 and, for a period. At the same time, at the moments of strobing, therefore, to get under (G | th and I go unchanged at the inputs of the second synchronous filter-variable initial charge level & 4 .. (|

0

potentials are approximately equal. So about; . Here, the frequency of the pulses at the output of the digital frequency synthesizer, for which the fifth output of the control unit 23 is used, is 1, is /, / o-

The charge of and the discharge of the first 10 and second And storage capacitors are relative to the average level L U. In the first time interval t, after the pulse arrives from the first counter 4, the first storage capacitor 10 is charged with the first power supply 14 of the first b. A nice 12 charge less current, and the second

O (1Sh11M

storage capacitor 1

/ 2 first accumulator. Capacitor 10 is discharged by the second block 16;

current. Therefore, at the end of the time interval t, the first storage capacitor 10 is charged before a high voltage than the second storage capacitor 11. In the | first time interval

current than the second storage capacitor 11. The end of the time interval ti corresponds to the time when the potential on the first storage capacitor 10 becomes less than the potential on the second storage capacitor I. After this time, the second time interval t begins, the first storage capacitor 10 It is supplied by the current of the first block 5, a bit larger than the current of the second storage capacitor 11. At the end of the second interval

the duration of the pulses on the first and third outputs of the control unit 23 (the delays of the first 31 and second 32 delay elements), and the duration of the inter1) time / 2 shafts is determined by the ratio of

for the first time interval i- and the magnitude of the currents at the outputs of the second charge unit 13 for the second time interval t-i.

To balance the values of charge and discharge currents of the first 10 and second 1

storage capacitors in the period of arrival of the pulses of the first counter 4 and, therefore, in order to get under (G | th), the initial level of charge & 4 .. (|

the first synchronous filter 6. Its inputs receive a voltage from the current-setting element 19 (made, for example, in the form of two field-effect transistors with combined drains, not shown), the value of which at the beginning of the time interval t is equal to UH, and the voltage source of the reference voltage 20. The first synchronous filter 6 by adjusting the magnitude of the charging currents in the first time interval t and the discharge currents in the second time interval ti ensures that the voltage UQ is equal to the voltage at the output of the reference voltage source 20.

As the first 6 and second 7 synchronous filters, filters constructed according to the differential scheme can be used.

Maximum synthesized frequency

output pulses / max: PG So

 1mi1 | g 2min

as the charge of the first 10 and second 11 storage capacitors and their discharge are formed by the first and second blocks 12, 13, 15, 16 of the charge and discharge working in the same modes, then 1 „„ / 2min min

/ -L -, .n

The minimum frequency is determined by the maximum permissible value of the time interval t, if we neglect the value of the time interval 1 1, „„. It is limited by the uncontrolled constant discharge time of the first 10 and second 11 storage capacitors due to the finite magnitude of the collector resistances of the transistors in the locked state and the final input resistance of the block 18 of the source repeaters on field-effect transistors. Taking into account the leakage resistance values, the minimum frequency can be several tens of Hertz and, therefore, the digital frequency synthesizer provides a significant overlap ratio.

Claims (2)

1. A digital frequency synthesizer containing serially connected first frequency code register and first counter with variable conversion factor, serially connected second frequency code register and second counter with variable conversion factor, first digital-to-analog converter and reference frequency generator, the output of which is connected to counting the input of the first counter with a variable conversion factor, characterized in that, in order to expand the range of synthesized frequencies, sequentially ennye first used, power supply can source reference voltage, the first synchronous filter, the first the charge unit and the first storage capacitor, the current-supplying element in series, the source follower unit, the differential amplifier, trigger and control unit, a second synchronous filter, a second charge unit, a second storage capacitor, a second power source, a first discharge unit, a second discharge unit, a second D / A converter and an OR element whose output is connected to the first control input of the first unit are also entered the charge, the first input of the element OR is connected to the first input of the control unit, the second input of the element OR is combined with the installation input in the "About second counter with a variable conversion factor, the first input of the second synchronous fil tra and connected to the output of the first counter with a variable-ratio conversion, second, third and the fourth outputs of the control unit are connected respectively to the first control input of the first discharge unit, to the first control input of the second charging unit and to the first control input of the second discharge unit, the counting input of the second A 5 counter with a variable conversion factor is combined with the control input of the first synchronous filter and with the control input of the second synchronous filter and connected to the fifth output of the control unit, the second input of which is connected to the second, 0 trigger output, the second input and the second output of the first synchronous filter are connected respectively to the output of the current supply element and to the second control input of the first discharge unit, whose information input is combined with the information input of the first charge unit and connected to the output of the first digital-analogue the converter whose input is connected to the output of the first frequency code register, the second control input of the second 0 of the charge unit is combined with the second control input of the second discharge unit and connected to the output of the second synchronous filter, the second input of which is connected to the output of the second counter with a variable conversion factor, information input 5 of the second charging unit is integrated by the Q information input of the second discharge unit and connected to the output of the second digital-analog converter, whose input is connected to the output of the second frequency code register, the first output of the first discharge unit 0 and combined with the first output of the first charging unit the first output of the second charging unit and the first output of the second discharge unit and connected to the first signal input of the source follower unit, the second output of which is connected to the second input of the differential amplifier, the second output of which o is connected to the second trigger input, the second output of the first charging unit is combined with the second output of the first discharge unit, with the second output of the second charging unit, with the second output of the second discharge unit, with the second input of the source followers unit and connected to the first output of the second a storage capacitor, the second output of which is combined with the second output of the first storage capacitor and connected to the zero potential bus, the input of the current supplying element is combined with the input of the first charging unit, with the input of the second charging unit, and connected to the output of the first power supply, the input of the first discharge is combined with the input of the second power supply unit and connected to the output of the second power supply. 2. A synthesizer according to claim 1, wherein that the control unit contains serially connected first element NOT and first element AND, serially connected first delay element, second the element AND and the element OR, sequentially, 1HH (:) the connected second delay element and the third element AND, successively connected to the second element) 1t NOT: and the fourth element 11. the second input of the first element H is combined with the second input of the second e. 1e.1.tenta AND with the input of the first delay element and is the first input of the control unit the second input of the third element AND with the second input of the fourth element And and with the input of the second delay element is the second input of the control unit unit, the input of the first element is NOT connected to the output of the second element AND, the second input of the element OR is combined with the input of the secondary) the element is NOT and is connected to the output of the third element AND, and the outputs of the first, second), third, fourth elements AND and the OR element are respectively the fourth, first, second, third and fifth outputs of the control unit.