SU1073857A1 - D.c.voltage converter - Google Patents

Abstract

CONSTANT VOLTAGE CONVERTER containing n series-connected capacitor-valve cells of voltage doubling, each of which between the input terminals includes a chain of consistently connected discharge and charge switches, the second terminal of which is connected to the connection point, the diode is connected to the first input and output pins of the cell, and the second input and output pins of the cell are combined, and the key management unit, which also includes Reducing the mass and dimensions and increasing the efficiency, the diode is connected between the first input and output cell terminals, the second capacitor terminal is connected directly to the first output cell terminal, and the key management unit contains a frequency divider with N-1 outputs, and the clock divider input is They are connected to the input of the keys of the first cell, and the outputs of the frequency divider are connected to the inputs of the keys of the corresponding subsequent cells. t: x): l

Description

The invention relates to electrical engineering and can be used in secondary power sources of low power equipment for converting low DC to high voltage.

A valve-capacitor DC voltage multiplier is known, containing a chain of matched successively connected discharge and charge switches connected between the input terminals, and a chain of two consistently connected diodes connected between the input and output terminals, and two capacitors, one of which is connected between the point of connection of the keys and the point of connection of the diodes, and the other between the output pins CiJ.

This converter only doubles the voltage. A series (cascade) connection of such voltage doublers is used to multiply the voltage more than twice.

The closest in technical essence to the present invention is a constant voltage converter containing N series-connected voltage doubled capacitor-cell cells, each of which has a chain of serially connected discharge and charge switches connected to the input terminals the connections of which are connected to the first output of the first capacitor, the second output of which is connected to the point of the sequential connection of two diodes connected between the input and output The output of the cell, and parallel to the output of each cell, the second capacitor 2 is turned on.

The presence of two capacitors and two diodes in each cell increases the mass and size of the transducer and reduces its efficiency.

The purpose of the invention is to reduce the weight and size and improve efficiency.

The goal is achieved by the fact that in a constant voltage converter, containing N series-connected capacitor-valve double voltage cells, each of which between the input terminals includes a chain of correspondingly-serially connected discharge and charge switches, to the junction of which the first terminal of the capacitor, the second terminal of which is connected via a diode to the first input and output terminals of the cell, and the second input and output terminals of the cell are combined, and the key management unit indicated Iodine is connected between the first

the input and output terminals of the cell, the second terminal of the capacitor is connected directly to the first output terminal of the cell, and the key management unit contains a frequency divider with N-1 outputs,

moreover, the input of the frequency divider is connected to the input of the keys of the first cell, and the outputs of the frequency divider are connected to the inputs of the keys of the corresponding subsequent cells.

FIG. 1 is a schematic diagram of the converter in FIG. 2 - voltage diagrams.

The converter (Fig. 1) is connected on the input side to the power source 1 and contains N voltage doubled 2.1-2.N capacitor-valve cells connected in series, i.e. A single 0 input is connected to the other input. Each cell has the first input pin 3, the first output pin 4 and the combined second input and output pins 5. Between the pins 3 5 and 5 are connected in series-connected keys (transistors, and between the pins 3 and 4 - a diode. The input of the keys is connected to the output 6. At the output of the converter, diode 7 is switched on and the load is shunted by the filtering capacitor 8. The control unit contains the master oscillator 9 and the frequency divider 10, the input of the frequency divider and the input from the key of the first cell connected to the output of the master oscillator, and the outputs The frequency bodies are with the inputs of the keys of the corresponding cells, with this between the connection point of the keys and the output 4 of each cell, the corresponding capacitor 11 is turned on.

FIG. 2 horizontally, the time intervals i from tg to the delay are set equal to the half-period of the input control signal. Top 5 down shows voltage plots at some points:

where is the voltage at the output of the master oscillator 9, at the input of the key of the first cell, at the 0 input the frequency divider

.

Ug is the voltage at the first output of the frequency divider, at the input of the second cell key (f / 2 |; 5 voltage at the second output of the frequency divider, at the input of the third cell key (f / 4); and - voltage at the third output of the divider. frequency, at the input of the key of the fourth cell, LL l "1 voltage on the capacitors -ftN of the corresponding cells, the voltage on the load. The converter operates as follows.

Let us assume that each capacitor is either fully charged from the previous cell, or completely discharged into subsequent cells. The drop in stresses on unlocked and leakage of locked elements is not taken into account.

The frequency divider operates in the pulse counting mode, i.e. the beginning of the periods of impulses coincide. The frequency division factor is 2. At zero amplitude of the input pulse, the key is unlocked and the capacitor is charged from the previous cells. With a single amplitude of the input pulse, the key is locked, i.e. the capacitor is connected in series with the previous cell and discharged into subsequent cells.

In the time interval t. (Fig. 2) all keys are unlocked and the capacitors of all cells are charged before the voltage U.J of the power source. At time t, the first key is locked, connecting the first capacitor in series with the power supply, and the capacitor of the subsequent cells is charged to double amplitude (2 vertically). The first cell capacitor is thus discharged. At time t, the first switch is unlocked, the second is locked, the capacitor of the first cell is charged from the power source, and the capacitor of the second cell, connected in series with the power source, is discharged to the capacitors of the subsequent cells and the capacitor 8, charging them to triple amplitude. At time tj.4, the key 1 of the first cell is again locked and the capacitor of the first cell is connected in series to the power transmission and, together with the power source and the capacitor of the second cell, is charged. ;. the capacitor 8 and the capacitors of the third and fourth cells up to four times amplitude. At the moment t -fl, the previous cycles are repeated, but already with the connection of the capacitor of the third cell, while

the fourth cell capacitor and the capacitor are charged in 8 steps to an eightfold amplitude. Finally, at time d.4, a fourth cell capacitor is connected, charging the capacitor 8 to 16 times amplitude. In a real scheme, taking into account residual voltage losses, the capacitors, as well as depending on the ratio of capacitances, increase in charge monotonously and, in the established diagram of the diagram, the voltage on the capacitors appears as indicated by a dotted line with a slightly smaller amplitude

five

where is the voltage at the load /

E. Voltage Power Supply 1;

N is the number of doubling cells.

In the next period, the circuit returns to its original state and the whole cycle repeats.

For effective operation of the device

5, it is desirable that the capacitors' capacitances decrease from the first stage to the last, and the diodes of the first stages have the smallest possible voltage drop. it

The requirement applies to other types of such voltage multipliers.

By adjusting the frequency of the generator 9, you can adjust the power

5 given to the load. The division factor of the divider frequency may be different, but not less than two of the neighboring cells.

A decrease in the number of diodes and capacitors made it possible with modern elemental base to improve the efficiency and weight and size parameters by 20-50%, depending on the number of cells. This is especially felt with low 5 volt primary power sources having a voltage in the order of a few volts.

Claims (1)

(54 1 DC-DC converter, containing both series-connected capacitor-valve voltage doubling cells, in each of which between the input terminals is connected a chain of successively connected discharge and charging keys, to the connection point of which the first output of the capacitor is connected, the second output of which is connected through a diode through a diode with the first input and output pins of the cell, and the second input and output pins of the cell are combined, and the key control unit, with the fact that, for the purpose of mind to reduce the weight and dimensions and increase the efficiency, the indicated diode is connected between the first input and output terminals of the cell, the second output of the capacitor is connected directly to the first output terminal of the cell, and the key control unit contains a frequency divider with N-1 outputs, and the input of the divider is connected to the key input of the first cell, and the outputs of the frequency divider are connected to the key inputs of the corresponding subsequent cells.