SU1541732A1 - Single-phase full-wave ac-to-dc voltage converter - Google Patents

Abstract

The invention relates to electrical engineering and can be used in secondary power sources. The purpose of the invention is to improve the weight and size parameters by reducing the total capacitance of the capacitors. The device consists of parallel-connected chains, each of which, except the first and last, is designed as a series-connected uncontrolled valve 2, a condenser 1 and an uncontrolled valve 3. The first chain consists of a condenser 1 and a valve 3, and the last is of a condenser 1 and valve 2. The cathodes of the valves 2 are connected via the control key 12 to the output terminal 19. The anodes of the valves 3 are connected via the control key 13 to the output terminal 20. Parallel to the first chain, a circuit is connected from the series-connected valves 9, 10, the cathode of the first of which is via counter-connected valves 5, 7 and the anode of the second through valves 6, 8, connected in the opposite direction with respect to valves 5, 7, connected to the input terminal 18. The anode of the valve 9 is connected to the common terminal 22. Block 15 The control provides four-stroke switching of keys 11, 12, 13 during the supply voltage period. The key 11 is connected by its leads between the anode of the valve 7 and the cathode of the valve 8. The device allows the capacitors to be charged from the network twice in each half-period and discharged to the load. In this case, the time of their discharge is less than a quarter of the period. The ripple frequency of the output voltage is 4F network. 2 hp ff, 5 ill.

Description

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The invention relates to electrical engineering and can be used in secondary power sources. The purpose of the invention is to improve the mass and storage parameters by reducing the total capacitance of the capacitors.

Figure 1 shows the structural diagram of the proposed device; FIG. 2 shows diagrams explaining his work; FIG. FIG. 3 is a block diagram of the control unit; 4 shows diagrams explaining his work; on fig.Z - block diagram synchronizer.15

The converter (Fig. 1) contains n chains, each of which, besides the first and last, consists of a capacitor 1 and two uncontrollable valves 2 and 3, and the first and last 20 - of a condenser 1 and valves 3 and 2, respectively, each the previous chain is connected to the next one via an uncontrolled valve 4, uncontrolled valves 5-10, control keys 25 11-13, a capacitor 14 and a control unit 15.

Uncontrolled valves 2 form a cathode group, the output (bus) 16 of which is formed by combined positive inputs and output of chains, and the valves 3 form an anode group, the output (bus) 17 of which is formed by combined negative inputs and output of chains. The input (phase) bus (input terminal) 18 of the transformer, the body through the valve 5 is connected to one output of the control key 11 and the anode of the valve 7, the cathode of which is connected to the cathode, JQ house of the valve 9 and the bus 16 which is connected via the control key 12 to the positive output bus (output terminal) 19 of the converter. In addition, the bus 18 through the valve 6 in the right-turn-on mode is connected to another output of the key 11 and the cathode of the valve 8, the anode of which is connected to the anode of the valve 10 and the bus 17, which through

connected to busbars 18 and 21, and outputs 23-25 to the corresponding control electrodes of controlled keys. The phase bus of the alternating voltage source U is connected to bus 18 and the neutral to bus 21. The load of the converter is connected to the common bus 22 by one end and the bus 19 or 20 by the other, depending on the desired polarity of the output voltage. In addition, if positive polarity of the output voltage is required, then

bus 20 must be connected to bus 22, and if negative polarity is required, then bus J 9 must be connected to bus 22.

The control unit J5 (FIG. 3) contains a synchronizer 26, a generator of 27 clock pulses (GTI), a counter 28, four comparators, a combiner 33, two matching cac 34 and 35, a delay 36 device Schmitt trigger 37, a trigger trigger 38 and a power source 39 .

The output 40 of the synchronizer 26 is connected to the R-input of the counter 28, the C-input of which is connected to the output of the GTI 27, and the output by the information bus 41 is connected to each comparator 29-32, to the other inputs of which reference numbers t ,, t7, t3 and t4, respectively. Outputs 42-45 of the comparators are connected by bus 46 to the inputs of the combinator 33, the outputs 47 and 48 of which are connected to the control electrodes of the controlled keys via the corresponding matching stages 34 and 35. The output 49 of the device 36 delay through the Schmitt trigger 37 output Tina 50 is connected to the input 51 of the combinational node 33 and to the input 52 of the starting trigger 38. In addition, the inputs 53 and 54 of the starting trigger are connected respectively to the outputs 40 and 55 of the synchronizer and the combinational node, input 56 which is connected to the exit 57 start trigger.

The synchronizer 26 (Figure 5) contains

the equal key 13 is connected to the negative 5Q Amplifier of the FIRMWARE 58, two identical output bus (with a negative output terminal) 20 of the converter. The capacitor 14 is connected between the tires 19 and 20. The anode of the valve 9 and the cathode of the valve 10 are combined and connected to a common bus (common output) of the converter formed by the combined input 21 and output 22 terminals (tires). Input block 15 control

The actual formers 59 and 60 pulses, the inverter 61 and the coincidence circuit 62. The output 63 of the amplifier-limiter 58 is connected via a pulse shaper 59 to one input of a coincidence circuit, and through a series-connected inverter 61 and a pulse shaper 60 to another input of a coincidence circuit 62.

0 5

0 Q 5

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connected to busbars 18 and 21, and outputs 23-25 to the corresponding control electrodes of controlled keys. The phase bus of the alternating voltage source U is connected to bus 18 and the neutral to bus 21. The load of the converter is connected to the common bus 22 by one end and the bus 19 or 20 by the other, depending on the desired polarity of the output voltage. In addition, if positive polarity of the output voltage is required, then

bus 20 must be connected to bus 22, and if negative polarity is required, then bus J 9 must be connected to bus 22.

The control unit J5 (FIG. 3) contains a synchronizer 26, a generator of 27 clock pulses (GTI), a counter 28, four comparators, a combinator 33, two matching stages 34 and 35, a delay device 36, a Schmitt trigger 37, a trigger trigger 38 and a source 39 nutrition

The output 40 of the synchronizer 26 is connected to the R-input of the counter 28, the C-input of which is connected to the output of the GTI 27, and the output by the information bus 41 is connected to each comparator 29-32, to the other inputs of which reference numbers t ,, t7, t3 and t4 respectively. The outputs 42-45 of the comparators are connected by bus 46 to the inputs of the combinator 33, the outputs 47 and 48 of which are connected to the control electrodes of the controlled keys through the corresponding matching stages 34 and 35. The output 49 of the device 36 delay through the Schmitt trigger 37 output Tina 50 is connected to the input 51 of the combinational node 33 and to the input 52 of the starting trigger 38. In addition, the inputs 53 and 54 of the starting trigger are connected respectively to the outputs 40 and 55 of the synchronizer and the combinational node, input 56 which is connected to the exit 57 start trigger.

The synchronizer 26 (Figure 5) contains

Amplifier switch 58, two identical pulse drivers 59 and 60, an inverter 61, and a matching circuit 62. The output 63 of the amplifier-limiter 58 is connected via a pulse shaper 59 to one input of a coincidence circuit, and through a series-connected inverter 61 and a pulse shaper 60 to another input of a coincidence circuit 62.

The keys 11-13 are controlled in accordance with the diagrams shown in Figures 2 and 4, where Uf and U are the voltage to be converted and its amplitude value; Un and U0 is the load voltage and its average value; i. - charge current of capacitors 1 (the current consumed from the primary source); t, and t p are the charge and discharge times of capacitors 1; T is the period of the voltage being converted.

Controlled keys 11-13 (Lig.1), limiting amplifier 58 (Fig. 5), matching cascades 34 and 35, power supply 39, combinational node 38, clock pulse generator 27, Schmitt trigger 37 and trigger trigger 38 ( Fig. 3) can be performed by known circuits on digital elements.

The Converter operates as follows.

The phase of the alternating voltage source is connected to the bus 18 (Fig. 1), and the neutral to the bus 21. Let the load require a positive polarity voltage relative to the neutral. Then the load is connected to tires 19 and 22, and bus 20 must be connected to bus 22 (if the load requires a negative polarity voltage relative to the neutral, then it must be connected to buses. 20 and 22, and bus 19 must be connected to bus 22). In the steady state, on capacitors 1 and 14 there is a voltage Cr whose polarity is indicated in Fig. 1, and the form on (Li 2 and 4.

From the time t, (FIG. 2) to the time tz, the controlled key II (FIG. 1) is open, and the keys 12 and 13 are closed. During charging t, the capacitors J are charged by the current i through the circuit: bus 18 - valve 6 - switch 11 - valve 7 - capacitors 1 connected in series through valve 4 - bus 17 - valve 10 - bus 21, and the voltage UH on the load is maintained a capacitor 14 discharged along the circuit: capacitor 14 — bus 19 — load — connected tires 22 and 20 — capacitor 14. From the time tg after the delay for fully closing the key 11 (FIG. 4), the keys 12 and 13 are opened, and all the capacitors 1 in parallel and simultaneously (each through its own discharge valves 2 and 3) are discharged to parallel but connected capacitor 14 and load on the circuit: capacitor 1 - valve 2 - key 12, bus 19, capacitor 14 and load - bus 22 and ping 20 connected to it - key 13 - valve 3 - capacitor 1, during the time tp . The form of the voltage on the recharging capacitor 14 and on the load will be as indicated in Figures 2 and 4. Considering the delay time t 5vd for fully closing the keys 12 and 13, the duration of this first cycle (cycle) is

5 pd-bit from time t to time t3 is equal to t y + t3elA + tp + t of the low-frequency amp - T / 4. From the moment t3 to the moment tj (Fig. 2) in the same positive half-period of the transformed voltage

0, the second cycle of operation is carried out similarly to the first. In the negative half-cycle of the voltage being converted, there will also be two cycles of charge — the discharge of capacitors 1. The converter's operation differs only in the supply circuit of charge current i, capacitors 1. In the third (from t s to t) and fourth (from t T to tg) cycles over t3. J capacitors are recharged

0 ij along the circuit: bus 21 - valve 9 — capacitors 1 connected in series through valves 4 — valve 8 — key 11 — valve 5 — bus 18. Thus, with one control key 11 and six uncontrolled valves 5-10 Two-wavelength type current conversion is provided with a common bus 21-22 for the input and output of the converter. In addition, for

0, the period of converted voltage is carried out for four cycles (tact) of charge - discharge, capacitors of the reactive part of the converter. The duration of one cycle is equal to T / 4, i.e.

5, the conversion frequency is four times the frequency of the voltage to be converted. This mode of operation of the converter is provided by the control unit.

o The control unit 15 (FIG. 3) operates as follows.

In the established mode, the synchronizer 26 at the moments of voltage transition of the network U1 (FIG. 4) through zero expresses the clock pulses that arrive at the input of the zero setting of the counter 28 and each counter of the network resets the counter. Its counting input receives pulses from the output of the GTI

27. From the meter outputs, the current count value A t, ..., A 4, through the information bus 41, goes to the inputs of digital comparators 29-32, to the other

the inputs of which are the reference numbers B. ,, ,, ..., B4, defining moments (t and t, t and t4 in Fig. 1) of the beginning and end of the charge of capacitors 1 (Fig.) at the level of 0.7 and, . At the moment of equality of the number of pulses from the GTI 27 through the counter 28, and the reference number (A., B ,; A2 B ,; Ae B, and A4 B -), each comparator generates a clock pulse (t1f t0, t3 and t4 Fig. 4) These pulses arrive at the combinational node 33, which generates control pulses of charge, discharge and delay (Fig. 4) of the corresponding duration. These pulses through matching cascades 34 and 35 control the operation of keys H-I3 (Fig. I).

In the steady state, the capacitor of the delayed device 36 to the voltage Un of the power supply source 39 and at the output of the Schmitt trigger 37 will be a low voltage level (Log. O), which allows the combinational node 33 to control the L-13 keys and hold the trigger trigger 38 in a steady state.

In a transient mode, when starting the converter into the network, the starting trigger 38 together with the Schmitt trigger 37 and the delay device 36 provides the charge to the capacitors J (Fig. 1) once each half-period of the network voltage, starting from the moment it passes through zero. The number of half-cycles of the network for outputting the converter to the steady state operation is determined by the constant time ™ or RC circuit of the delay device 36. During the transient process, the supply voltage Un increases and with a delay the voltage on the capacitor of the delay device 36 rises. At output 50 of the Schmitt trigger, there is a high voltage level (Log.1). This unit on entry 51 prohibits

the combinational node 33 controls the keys 11-13, removes the control signals from them, and enables input 52 of the start trigger 38, which is transferred to unity state by a signal from the synchronizer 26 through input 53, and a signal from the output 43 of the comparator 30 through the combinator node 33 (exit 55) through 54 translates

50

50

- 0 5 0

five

c to zero state. This impulse is transmitted through the combinational node and the matching stage 34 to the controlled key 11, thereby ensuring a smooth increase in the current consumed from the network, i.e. soft start converter.

Synchronizer 26 (Lig.5) works as follows.

The input 18 of the amplifier-limiter 58 receives a variable network voltage. From its output 63, the rectangular voltage is transmitted to (short pulse width driver 59, generating a positive voltage drop once per network period. The rectangular voltage inverted by inverter 61 is transmitted to another driver 60. The signal at its output corresponds in time to a negative voltage drop across the amplifier-limiter. Both short pulses are combined by a coincidence circuit 62, the output 39 of which is also the synchronizer output. Rope pulses (Fig. 1) correspond to the network voltage passing through zero.

Thus, the proposed converter is a full-wave four-stroke. Its conversion frequency is two times higher than that of the known, and the discharge time of capacitors is two times less. Therefore, with the same output parameters, the total capacity of the reactive part of the proposed converter as compared to the known two times and, therefore, less mass and volume of the reactive part and the converter as a whole,

In addition to improving the weight and size parameters, the proposed converter is highly reliable, since the number of controlled elements in the power section is reduced and a soft start is ensured when the converter is turned on to the network. The pulsation frequency of the output voltage at the first harmonic is 4f of the network. Therefore, with further smoothing of the pulsation, the additional filtering device has a smaller mass and volume.

Claims (3)

1. Single-phase, two-half-cycle variable voltage converter y1 5 neither permanently, containing the first input and output and the second input and output terminals for connecting, respectively, the power source and load, the voltage dividing unit, consisting of sequential chains, each of which, except the first and last, consists of series-connected the first uncontrolled valve, the condenser and the second uncontrolled valve, and the first and last chains consist respectively of a series-connected condenser with the second uncontrolled valve and a condenser with the first uncontrolled equal valve, and the opposite plates of the capacitors of adjacent chains are connected through the third uncontrolled valve, the cathodes of the first valves of the above chains are combined into a common point connected through the first controlled key to the first output terminal, the anodes of the second valves of the specified chains are combined into a common point connected through the second controlled key to the second output terminal, as well as the output capacitor connected between the output terminals, one of which is combined with the second input terminal, to form a common the output, the fourth uncontrolled valve, cathode connected to the common output, the third controllable key and the controllable key control unit, which ensured during each period of the supply voltage the alternate switching of the controllable keys in accordance with the charge-discharge cycles of the division unit capacitors voltage, so that, in order to improve the overall dimensions by reducing the total capacitance of the capacitors, the output of the free capacitor plate of the first chain of the dividing unit The connector is connected to the common connection point of the cathodes of the indicated first uncontrolled gates, the output of the free capacitor plate of the last chain is connected to the common connection point of the anodes of the specified second non-adjustable gates and the fifth, sixth, seventh, eighth and ninth uncontrollable gates are added the cathode of the fifth valve is connected to the first input terminal and to the anode of the sixth valve, the cathode of which is connected to the cathode of the eighth valve and 0 five 0 five 0 five 0 five 0 five 32Y  one of the terminals of the third controlled key, the other terminal of which is connected to the anodes of the fifth and seventh valves, the cathode of the last of which is connected to the cathode of the ninth valve and from the gate. It connects the cathodes of these first valves, the anode of the ninth valve is connected to the cathode of the fourth valve, the anode of which is connected to the anode of the eighth valve and the common connection point of the anodes of these second valves, and the control unit provides four keys for each period. 2, the converter according to claim. 2, wherein the control block comprises a synchronizer, a clock pulse generator, a counter, four comparators, a combinational node, two matching stages, a delay device, a Schmitt trigger, a trigger trigger and a power source, and the synchronizer input is connected with the second input bus of the converter, and the output with the P input of the counter, the C input of which is connected to the output of the clock generator, and the output of the counter of the information bus connected to each comparator, the other inputs of which are connected to the source of reference numbers, while the outputs of all the comparators are connected to the corresponding inputs of the combinational node, the outputs of which are connected to the control electrodes of the corresponding controlled keys through the matching stages, the output of the power source is connected to the input of the delay device and whose output through the Schmitt trigger is connected to one of the inputs of the trigger trigger and one of the inputs of the combinational node, one of the outputs of the combinational node is connected to another input of the trigger trigger, the output of which is connected to another input of the combinational node, and the synchronizer output is connected to the third start input trigger 3. The converter according to claim 2, characterized in that the synchronizer contains an amplifier-limiter, two identical lenses, pulses, an inverter and a matching circuit, the input of the amplifier-limiting element forming the synchronizer input, and the output through the first pulse shaper is connected to one circuit input 1 154173212 coincidence, the output of which forms the second implant shaper - with the synchronizer output, and after the other input of the specified circuit, the coincidently connected inverter and day coincide. M f t t W, L tp J and FIG. 2 gz II f i -it-tir-ti-ilf-itiiii, 11 and and and j and IN; ft, ba, tt tfh q t CY-U i p n Pg4pPg Pg-Pg-iflr II eleven eleven tttt M II C K II I i IIIII IIIIII eleven eleven tt FIG. s