SU1403287A2 - Frequency converter - Google Patents

Abstract

The invention relates to a converter technique. The aim of the invention is to improve the quality of the output voltage. The device contains two storage capacitors 1, 2, which through the key elements 5, 6, 15, 16 and the keys 74.1 ... 74.p are connected to the secondary windings 76.1 ... 76.P of the matching cable 75. Voltage But pointing to points 3, 4 varies in proportion to the amplitude of the driving voltage. This increases the accuracy of the formation of the output voltage in the intervals of the transition of the master voltage through zero. 1 h. n. f-ly, 5 ill.

Description

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: The invention relates to converter technology, in particular to transformerless converters of alternating voltage of one frequency to alternating voltage of another frequency.

The aim of the invention is to improve the quality of the output voltage.

FIG. 1 shows a diagram of a frequency converter; in fig. 2 is a control circuit of fully controllable key elements and AC dongle keys, E extending into the control unit; on .fig. 3 and 4 are voltage diagrams for individual circuit elements; in fig. 5 is a control circuit of additionally introduced AC switches included in the control unit.

 The frequency converter (Fig. 1) contains two locking capacitors 1, 2, the first combined plates of which are connected to points 3, 4 through the first 5 and Btoroy 6 key elements, made: in the form of anti-parallel connected | fully controlled valve elements 7, 8 and 9, 10, and the second capacitor plates with the first 11 and 12 power electrodes of the alternating current discharge switches 13 and 14 and with points 3, 4 through the third 15 and fourth 16 key elements made in the form of an anti-parallel connected fully controlled valve elements 17, 18 and 19, 20, and block 21; controls, the combined plates of storage capacitors 1, 2 are connected to the first 22 output terminal, and the second power electrodes 23, 24 of the keys 13, P4 of the alternating current are connected and connected to the second output pin 25.

In this case, control unit 21 contains: (Fig. 2) the first formative; 1 26 rectangular voltage connected to the input terminals, and the outputs to the corresponding first inputs of the first pair of two-input logic elements And 27, 28 and to the output of the first phase shift 1, it has circuits 29, the outputs of which are connected to the second rods of a pair of logic elements AND 27, 28, the first pair of three-input logic elements AND 30, 31 connected by their first and second inputs to the corresponding outputs of the aforementioned driver 26 and two amplitude comparators 32 , 33, in They are connected with different minimizing capacitors 1. 2 and the source 34 of the driving voltage, as well as the second pair of three-input / jujik elements And 35, 36, the first and second inputs of which are connected to the corresponding outputs of the first pair of two-input logic eleme {1t and 27, 28 and to the outputs of a pair of logical elements HE 37, 38, the inputs connected to the corresponding outputs of the specified A. amplitude comparators

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32, 33, the first and second pairs of two-input logic elements OR 39, 40 and 41, 42, the outputs of which are connected to the control electrodes of the key elements 8, 20; 10, 18; 9, 17; 7, 19; the third pair of three-input elements And 43, 44, connected by their first and second inputs to the corresponding outputs of the first pair of two-input logic elements And 27, 28 and to the outputs of the pair of logical elements HE 37, 38,

10 inputs connected to the corresponding outputs of the indicated amplitude comparators 32, 33, the first and second pairs of two-input logic elements OR 39, 40 and 41, 42, the outputs of which are connected to the control 12 l ju1, the electrodes of the key elements 8, 20; 10.18; 7, 19; the third pair of three-input elements And 43, 44, connected by their first and second inputs to the corresponding outputs of the first pair of two-input logic elements And 27, 28 and to the outputs

20 pairs of HE elements 37, 38, the fourth pair of three-input logic elements AND 45, 46, connected by their first and second inputs to the corresponding outputs of the first driver 26 and the specified amplitude comparators 32, 33, the second phase-shifting circuit 47 and the second driver 48 rectangular voltage, the input of which is connected to the source 34 of the driver voltage, and the output to the second phase-shifter circuit 47, the second and

30 third bins of two-input logic elements AND 49, 50 and 51, 52 connected by inputs to the corresponding outputs of the second phase-shifting circuit 47 and the second rectangular voltage regulator 48, and outputs to the third inputs of the mentioned three-input logic elements And 30, 31, 43, 44, 35, 36, 45, 46, the outputs of which are connected to the corresponding inputs of the mentioned two-input logic elements OR 39-42, the fourth and fifth pairs of the two-input logic elements And 53, 54 and 55, 56 The inputs of which are connected to the various outputs mentioned form spruce 26, 48, the third pair of two-input logic elements OR 57, 58., whose inputs are connected to the outputs of the fourth and fifth pairs of two-input logic elements And 53-56, and the outputs to the control electrodes of the alternating current discharge keys 14, 13.

On fi1. 3 set voltage 59

50 mains supplied to the input pins, the voltage 60 formed at the output of the source 34 of the given voltage, the voltage 61 at the output outputs of the converter, the voltage 62 and 63 obtained at the outputs of the first driver 26 of the direct voltage 55, voltage 64 , 65, forwarded. Worlds at the outputs of the first phase shifting circuit 29, output voltage 66, 67

the second driver 48, the output voltages 68, 69 of the second phase-moving circuit 47, the voltage 70-73, applied to the key elements 9, 17; 10, 18; 7, 19; 8, 20, respectively, from the outputs of the two-input logic elements OR 41, 40, 42, 39.

Into the frequency converter (Fig. 1), n alternating current switches 74.1 ... 74.P and matching transformer 75, the ends of the primary winding of which are connected to the input terminals, n secondary windings 76.1 ... 76.P, are connected in series and the first end the first 76.1 secondary winding is connected to the 4th point of the connection of the second and fourth fully controlled key elements 6, 16, and the second end of the nth secondary winding 76.p and (n-1) intermediate taps to the first power electrodes of the specified switches 74.1 ... 74.P AC, the second power The rods of which are combined and noxi-connected to the point 3 of the connection of the first and third fully controlled key elements 5, 15.

FIG. Figure 4 shows the input voltage UBX 77 at the input pins, which is supplied to the primary winding of the matching transformer 75, the output voltage Uj-4 78 between the points 3-4 circuits and dashes - the output voltage UBI. "At the output pins 22- 25 converter, which sets the voltage 79 Uslt).

FIG. 5 illustrates the rectifier 80 additionally introduced into the control unit 21 with a smoothing filter 81 associated with an auxiliary secondary winding 76. (n + 1) matching transformer 75, the first chain of series-connected voltage divider 82.1, amplitude comparator 83.1, synchronous RS- trigger 84.1 and power amplifier 85.1, (p-1) chains of series-connected voltage divider 82.j (82.2 ... 82.P), amplitude comparator 83.J (83.2 ... 83.p) logic element of unequality 86 .j (86.2 ... 86.P), synchronous RS flip-flop 84.j (84.2 ... 84.P ) and the power amplifier 85.j (85.2 ... 85.P), the shaper 87 clock pulses, the input of which is connected with the auxiliary winding 76. (n + 1) of the matching transformer, with all the inputs of the voltage divider 82.1. ..82.P are connected to the output of a smoothing filter 81, the inverting inputs of amplitude comparators 83.1 ... 83.P - with the output of the source 34 of the driving voltage, the non-inverting input of the j-ro amplitude comparator 83.j (... n) - the output of the j-ro voltage divider 82.j, the first input of the j-ro logical, inequality element 86.j (j 2 ... n) - with the output of the (j-1) th amplitude comparator 83. (j - 1) and R-BXO0

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home j-ro synchronous rs-tpnrrepa 84.j. the second input of the j-ro logic element of inequality 86.j (... n) - with the output of the j-ro amplitude comparator 83.j, S-BXO.I of the first synchronous RS flip-flop 84.1 - with the house of the nerve amplitude comparator 83.1, and S - inputs of the rest (p-1) ciinxpomnjix RS-flip-flops 84.2 ... 84.p - with corresponding HUiMH outputs of logic elements of unequalities 86.2 ... 86.p, R-input of the first synchronous RS-flip-flop 84.1 - with output of the logic element the unequalities 86.2 of the second chain, the j-ro input of the power amplifier 85.J - with the j-ro output of the synchronous RS-flip-flop 84.j, and the output - with the j-ro control electrode of the complementary The newly entered AC key 74.j.

The frequency converter operates as follows.

When the mains voltage is applied to the primary winding of the matching transformer 75, the rectifier 80 receives the alternating voltage of a corresponding amplitude, which is then rectified and the smoothing filter 81 is eliminated from the spectrum of the incoming voltage, which is harmonic components. A constant voltage from the output of the filter 81 is supplied to voltage dividers 82.1 ... 82. p. The output voltage of the voltage divider 82. p is chosen larger than the amplitude of the driving voltage with the minimum voltage of the output voltage, since the output voltages of the voltage dividers depend on the amplitude of the voltage of the input network. The output voltage of the divider 82. (n--) is set to 1/2 U., m.5, where Uvm. - the amplitude value of the drive voltage U} (,), the output voltage of the divider 82. (n-2) - 1/4 U, .MJ, the output voltage 82. (n-3) - 1/8 lJ.,. 7 "-j, i.e., the high voltage of the voltage dividers is halved. At the outputs of the amplitude comparators, logical units are formed in the j1 transition interval of the master voltage zero. The logical element of unequalities forms a logical unit on the output only if there is a logical unit and a logic unit at the inputs. one . Therefore, in the interval D t at the outputs of all elements of unequal form of fornrugs, logical zeroes. At the same time, a logical unit is supplied to the S-input of the nerve synchronous RS-flip-flop 84.1 at the time of arrival of a clocked nm11ul1) from the output of the formator 87 clocked pulses, which ensures the receipt of these pulses at the time the input voltage passes through zero. The logic unit from the output of the RS flip-flop 84.1 through the power amplifier 85.1 nosgupast PA switch on the key rt.i.

which provides the connection of winding 76.1 to points 3-4. In this case, the R-inputs of the flip-flops 84.2 ... 84.P receive logical units and set them to a state with a logical zero at the output. The first rectangular voltage driver 26 forms rectangular voltages 62, 63, which are in phase with the voltage 59 of the input network. The first phase-shifting circuit 29 forms, at the output of the voltage 64, 65, shifted relative to the voltages 62, 63 by 90 el. hail. The second rectangular voltage driver 48 at the outputs generates rectangular voltages 66,; 67 that are in phase with the master voltage from (1), which is generated by the generator: 34. The second phase-shifting circuit 47 ensures that the outputs of the voltages 68, 69 are shifted relative to the voltages 66, 67 by 90 el. hail. The outputs of the logic-NecKHx circuits AND 49, 50, 51, 52 are formed Alogical units in the intervals of coincidence of logical units 67, 69; 66, 69; 66, 68; | and 67, 68. The control pulses 71, arriving at the transistors 10, 18, are formed at the output of the AND 31 logic element, to the input of which pulses 62 are received, the logical unit from the output of the AND 50 logic element in the time interval to- (t, -f

+) and the signal from the amplitude output

: comparator 32. Note that in the time interval., the alternating current discharge key 14 is turned on, and capacitor 2 is connected: To output pins 22-25 and provides: power to the load. Turning on the transistor IpoB 10 and 18 ensures the charge of the storage capacitor 1 to a value corresponding to a predetermined voltage. At the moment | equalizing the driver voltage from (1): and the voltage proportional to the voltage across the capacitor 1, the amplitude comparator provides a logical zero at the output, which leads to the switching off of the transistors 10 and 18. In the time interval t , -1 to the load is connected to the prepared storage capacitor 1 by switching on the alternating-current bit 1.3 (the alternating-current key 14). The control pulse 73, the front of which coincides with the moment of input voltage crossing through zero, provides switching on of transistors 8, 20. The specified control pulse is formed at the output of the logic element And 30, the inputs of which receive pulses 63, pulses from the output of the logic element And 50 and c output of the amplitude comparator 33. The switching off of the indicated transistors occurs at the moment of equality of the driving voltage and voltage proportional to the voltage of the charged capacitor 2 due to the formation of a logic zero Exit AM0

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capacitor comparator 33. In a similar way, the control pulses of the remaining transistors 17, 18, 7, 8, 9, 10, 19, 20 are formed. When the driving voltage reaches (1) the corresponding value of the output of the additionally introduced amplitude comparator 83.1, a logical zero is formed, after which, at the output of the logic element of ambiguity 86.2, a logical unit is formed, which, on arrival of the clock pulse from the output of the driver 87, ensures the switching of synchronous RS-flip-flops 84.1 and 84.2. In this case, a logic unit appears at the output of the trigger 84.2, which turns on the second AC key 74.2, thereby increasing the voltage used to charge the storage capacitors. Switching the additionally introduced alternating current switches only at the moment when the input voltage passes through zero prevents additional overloading of the key elements 5, 6, 15, 16 with respect to the current. In this case, the control of key elements 5, 6, 15, 16 does not depend on how the winding of the matching transformer is connected to currents 3-4. As the amplitude of the driving voltage increases, synchronous RS-flip-flops are switched with subsequent sequence numbers and, therefore, alternating current switches 74.3 ... 74.p. Features of control of key elements in the intervals of decreasing the amplitude of the driving voltage, when it is necessary to reduce the amplitude of the output voltage 61, are as follows. In the time interval, the control pulse 72 is supplied to transistors 7, 19, and the pulse front coincides with the instant of maximum amplitude of the input voltage, which ensures the limitation of the maximum current through key elements 5, 6, 15, 16. The control pulse 72 in the time interval t, -tg is formed on the output of the logic element AND 36, the inputs of which are connected to the output of the logic element AND 51 and the output of the logical element HE 38, connected to the amplitude comparator 33. The cut of the control pulse 72 is determined by the moment of equality of direct voltage Uj (t) and a voltage proportional to the voltage across the capacitor 2. The voltage pulse sequences 70-73, po- ctypayupJ, and e respectively to the transistors 9, 17, D), 18; 7, 19, and 8, 20 graphically illustrate the switching sequences of these transistors. At the same time, the uncirculated impulses arrive at the transistors during the formation of a part of the output voltage increasing in amplitude, and blackened during the formation of a part of the output voltage decreasing in amplitude.

Thus, the introduction of additional elements into a known frequency converter improves the quality of the output voltage, i.e., the reproduction accuracy of the drive voltage U3 (t) by increasing the accuracy of the formation of the output voltage in the transition intervals of the reference voltage through zero. This is achieved by varying the voltage applied to points 3-4, in proportion to the amplitude of the driving voltage, which reduces the effect of the turn-off time of key elements on the fidelity of the driving voltage. In this case, the total number of turns of all secondary windings of the matching transformer is chosen from the ratio

iWi Cs- W ,. -,, .- We.x

where Kj 1,1 -1,2 - the safety factor;

W is the number of turns of the primary winding of the matching transformer;

Ts.TE.1. / X Ji.w.By- the amplitude value of the voltage at the input and output pins, respectively.

The voltage of series-connected all secondary windings 76.1 ... 76.P participates in the formation of voltage from 0.5 1 1tvp to Uint.ax when the state of the AC switch is 74.p. The safety factors are chosen from the condition of supplying the capacitor charge 1, 2 to the maximum value as a maximum for a quarter of the input voltage period.

The ratio of the number of turns (voltages) W (j.n) (+ 1) -th secondary winding of the matching transformer is related to the number of turns J-X of the previous secondary windings by the ratio

WQ.,) | Wi,

where Wj is the number of turns of the i-th secondary winding of the matching transformer.

If we take the number of turns of the secondary winding per unit, then the WTU. (: Wugh .::,:.,: .S 1: 1: 2: 4: 8 ... Such a ratio of the turns allows in each subrange m - between switching adjacent AC switches 74. (p-1) and 74.p, increase the voltage amplitude at points 3-4 by two times, thus ensuring a more accurate reproduction of the drive voltage at its zero-crossing intervals.

Claims (2)

1. The frequency converter according to the author. St. No. 1205240, characterized in that, for the purpose of increases the quality of the output voltage, additionally introduced n AC switches and a matching transformer, the ends of the primary winding of which are connected to the input terminals, n the secondary windings are connected in series and the first end of the first secondary winding is connected to the junction point of the second and fourth fully controlled key elements, and the second end of the pth secondary winding and  (p-1) intermediate taps — to the first power electrodes of the indicated AC switches, the second power electrodes of which are combined and connected to the junction point of the first and third fully 5 controlled key elements, and the control unit is additionally equipped with a rectifier with a smoothing filter connected with the auxiliary secondary winding of the matching transformer, the first chain of series-connected voltage divider, amplitude comparator, synchronous RS-trigger and power amplifier, ( 1) chains of series-connected voltage divider, amplitude comparator, logical element of inequality, synchronous RS flip-flop and power amplifier, shaper clock Mykh pulse input of which is coupled to the auxiliary winding of the matching transformer, all inputs voltage dividers 0 connected to the output of the smoothing filter, the inverting inputs of the amplitude comparators - with the source output for / auxiliary voltage, the non-inverting input of the j-ro amplitude comparator - with the output of the j-ro voltage divider, the first inputs of the j-ro logic element of unequality the output (J-1) of the amplitude comparator and the R-input of the j-ro synchronous RS flip-flop, the second input of the j-ro logic element of unequality - with the output of the j-ro 0 amplitude comparator, 8-input of the first synchronous RS-flip-flop - with output of the first amplitude comparator, and S-inputs of the rest (n-1) synchronous RS-flip-flops - with the corresponding outputs of the logic elements of unequality, R- input of the first synchronous RS-flip-flop - with the output of the logic element of unequalities of the second chain, the j-ro input of the power amplifier - with the j-ro output of the synchronous RS-flip-flop, and the output from the control 0 j-ro electrode additionally introduced key AC. 2. A frequency converter according to claim 1, characterized in that the number of turns of the W (j + l) (j + l) -th secondary winding of the matching transformer is chosen from the co5 ratio five V (j + l) .2.ch,  -the number of turns of the i-th secondary, where K, 1.1-1.2 - the safety factor; windings of the matching transformer-W - the number of turns of the permator, the primary winding of the match, the total number of turns of all the secondary transformer; windings of the matching transformer b, .Bx - amplitude value choose from the ratio voltage on the output and input pins, respectively. iwi in. Kf voltage on the output and input pins, respectively. CPU g KPPPPPPPPPPPPPPPPFPPPPP-T ППЛПЛППППППППППППППППППППППППП f ppppppppppppppppppppppppppppppppppppppppp, 55 1ПППППППППППППППППППППППППППП1 Si S3 it o t, fjifirK fl AND D nun iuMjftjjfjs , Ws it "iun nnn t, i, tf PDP CHOPPP POYUD 77 Fy (to gv (s, 6 " g / on S 7 / F7 rajs Sr 7 / HaS.ZO setting nr / H1 /)