SU1554096A1 - Bridge inverter - Google Patents

Abstract

This invention relates to the field of electrical engineering. The goal is to improve the quality of the output voltage. The device contains three half-bridges of controlled keys 1 - 6, to the output terminals of which the primary winding is connected, consisting of section 7 and 8 of the primary winding of the output transformer 9. The control unit contains the master oscillator 10 connected to the output of the N-channel pulse distributor 11. The duration of the steps that form the output voltage is determined by the number of channels of the pulse distributor 11. The spectral composition, and hence the value of the harmonic coefficient, is determined by the ratio of the numbers of turns of sections 7, 8 per the primary winding of the output transformer 9, the most optimal value of which is equal to 1, 43. 2 Cp f-ly, 2 ill.

Description

The invention relates to electrical engineering and can be used in power supply and electric drive systems to convert a DC voltage into an alternating sinusoidal voltage.

The purpose of the invention is to improve the quality of the output voltage.

FIG. 1 is a schematic diagram of an inverter; in fig. 2 - timing diagrams, on the basis of the principle of its operation and the formation of the output voltage.

The bridge inverter contains three half-bridges of controlled keys 1-6, the keys of the first 1.2 and third half-bridges are made in the form of alternating current keys, and the second half-bridge 3.4 - in the form of controlled key elements that are counter-parallel (for example - transistor) and a diode. The output windings of the half switches of switches 1-6 of the inverter are connected to the primary winding, which consists of sections 7 and 8 of the output transformer 9. The inverter control unit contains a master oscillator 10 connected by an output to the input of the N-tap pulse distributor 11. On FIG. 1 for example, pulse distributor 11 is shown as complete semiconductor () in the form of seven IK-flip-flops 12-18 connected in series with QQ QzQii Q7Qi paraphase outputs connected to a six-channel logic node 19. The outputs K, M ,, ..., M5Kz logical node 19 through the amplifier-decoupling node 20 is connected with the control inputs M, M, ... of the respective control keys. Connection between outputs Q, 0 ,, ... , PtP7 IK-triggers 12-18 of the pulse distributor 11 and the control inputs of the keys I-6 are implemented by the logical node 19 and are determined by the following logical expressions

five

0

five

0

five

0

five

0

five

M, o, o, o4o6q7. m, p,

Mi-OjQ + Qe + OgQ,, P4 + p4p6 + p6p M, Pg04 + pgp6 (. + 01Q6

The internal structure of the logical node 19 may be different, depending on the type and range of chips used. For example, the one shown in FIG. I variant of the logical node 19 implements the specified logical expressions based on the elements of NAND. In this case, the channel for generating the control signal Ml (Ml) contains two logical elements 2И-НЕ 21, 22 (23, 24), the inputs connected to the outputs of the pulse distributor 11 so that the connections between them are defined by logical expressions : at the output of the logical element 2И-НЕ 21 - Q, Q4 (23 - Р, p «.), at the output of the logical element 2И-НЕ 22 06р7 (24 -). The outputs of the logic elements 2I-NOT 21, 22 (23, 24) are connected to the input of the logic element ZI 25 (26), to the third input of which the output O is connected, (670 pulse distributor 11. At the output of the logic element ZI 25 (26) it forms signal

M, 0 (26-M, P,

The logical node channel 19, designed to form the control signal M2 (M2) of key 3 (4), contains a logical element 2I-NO 27 (28), the inputs of which are determined by the logical expressions: 2I-HE 27 0 .4P6 (28 - p4p6). I

The output of the logic element 2И-НЕ 27 (28) is connected to one of the inputs of the logical element ZI-HE 29 (30), the remaining inputs of which are connected to the outputs of the said logic elements 2И-НЕ 21, 22 (23, 24) so that its output will generate a signal, definable by the expression, 040 "p60607, This is

Life is identically equal to the minimized logical expression H2 Q O +0 06 + 060. At the output of the logical element ZI-NOT 30, a control signal will be generated, defined by the logical expression

ОЖ 0 7НР} 04 + 0 б -) - ЧБР7- To generate the control signal МЗ (МЗ) with key 5 (6), logic node 19 includes two logical elements 2И-НЕ 31 and 32 (33, 34), with outputs connected to the inputs of the third logic element 2I-NOT 35 (36). The output of the latter forms the output of the logic node 19 and is associated with the control input of the 5 MZ key (6 - MZ). The connections between the outputs of the pulse distributor 11 and the inputs of the logic elements 2I-NO 31, 32 (33, 34) are defined by the following logical expressions: the output of the logic element 2I-NOT 31 -,. (33 - (04) at the output of logic element 2И-НЕ 32 - Ог06 (34 - 0Z06). At the output of logic element 2И-НЕ 35 (36), thus, a signal will be generated by a logical expression .- Q2.Q6 ( 36 - M3 q CVQ Q 0264-K) zQ6).

The principle of operation of the converter is explained by the timing diagrams shown in FIG. 2. This drawing shows the U - signal from the output of the master oscillator 1, which synchronizes the operation of the converter. The sequences of rectangular symmetric pulses U, 4-U, | g () were obtained at the outputs of the pulse distributor 1I. The phase shift between the pulse sequences is 1/2 NT (in Fig. 2 -), where T is the period of the inverter output voltage. After the corresponding logical operations on the pulse sequences of the Pz-O pulse are performed, new pulse sequences Ml, M1, ..., MV, MV will be obtained at the outputs of logic node 19. The number of each logic element 21-36 corresponds to an index of a sequence of pulses, some of which are represented in FIG. 2. After amplification and galvanic isolation of the received sequences of control pulses, carried out with the help of an amplifier and control node 20, signals Ml, M1 ... MZ, MZ arrive at the control inputs Ml,

ten

20

25

5540% 6

W ... MZ, MZ keys 1-6 of the inverter. As a result, keys 1-6 switch according to a predetermined algorithm, and on the windings of the transformer 9 a step voltage with a zero pause of type V will be formed. The ratio of the numbers of turns W and W2 of the primary windings 7 and 8 of the transformer 9 must be in the range of 1: K, where, 43. In this case, the height of the individual steps of the output voltage curve will also vary: for example, when the height of the first 15 steps is V, 0, 5 V, x, and the second step, at, 25. , 44VMaKC; , 8UA, siss (Fig. 2a), at, 43 V, 0.4MVMaKC; Vz fe0, (Fig. 2b). The duration of these feet can also be set differently and is determined by the number of channels of the pulse distributor 11. When the duration of the pause, the first and second feet are equal to 1/14 T.

The proposed inverter allows, without complicating the structure of the power section of the converter, to reduce the value of the harmonics of the output voltage K /. The spectral composition, and therefore the value of K-, is determined by the parameters K and N. So, at, 25 and,, 1302, and at, 43 and K, 0.1184.

Claims (3)

1. A bridge inverter containing three half-bridges of controllable switches connected to the input terminals of the inverter in parallel, and an output transformer, the primary winding of which is divided into two sections with a ratio of turns in them equal to K, where K 1 is the extreme conclusions of this the windings are connected to the output pins of the first and third half-bridges of controllable keys, made as AC keys, and the output output of the first half-bridges is connected to the output of a section with a smaller number of turns, the primary winding is connected to the output outputs of the second half-bridges of controlled keys, as each of which used a counter-shunt transistor (with a diode turned on, and a control unit consisting of a master oscillator connected in series, an N-channel pulse distributor, where 6, and a logical node whose outputs are connected to the control inputs of the corresponding switches, characterized in that , in order to improve the quality of the output voltage, the value of K does not exceed 1.43, and the pulse distributor is made in the form of N serially connected IK triggers with paraphase outputs .0, Q "Q4C} j, ..., QNQN and with combined counting at odes connected to the output of the master oscillator and logic and communication between its inputs and outputs are arranged to provide the following logical expressions: , Q, Q4Qn-QN, And, Q, QiQ4Q ± -, QNi M4-Q, Q4 + Q4Qti-i + QH-iQNt Mz-q, q4 + Q4Qn -, + QiHQNi Mj-q -KhqN-i M, q2q4 + qiQn-i where M,, M, Mg, Mg, M3, Me- signals at the control inputs of the control keys, respectively, of the first, second and third half-noise. stop 2. The inverter according to claim 1, characterized in that, in order to minimize the harmonics of the output voltage, NB9 and K are adopted 1.43. 3. The inverter according to claim 1, characterized in that, in order to minimize the rated power of the L-shaped LC filter's inverter included in the output, 25 is adopted.