SU1358055A1 - Device for controlling d.c.to quasisinusoidal voltage converter with pulse-width modulation - Google Patents

Abstract

This invention relates to electrical engineering and can be used in static converters. The purpose of the invention is to improve the energy performance. The device for controlling the converter generates an output voltage that is not distorted by the load response at the lowest control power provided by limiting the duration of the control signals of the keys of the three-phase bridge inverter. In this case, it is possible to completely eliminate the counter-switching switching of its keys, which is especially important with transistor variants of building the power converter (and, as a result, eliminating the possibility of through-currents), as well as reducing the total number of switching. 2 Il. (Q CO SP 00 ate SP

Description

one

1358055 2

The invention relates to an electric 26, and a third input to the output of a three-phase polarity sensor 14. an output current of an inverter.

technology, namely, converter technology, and can be used in the construction of both centralized sources of secondary power supply (IHE) with sinusoidal output voltage and decentralized IHE used in the projection between the outputs of the distributor 8 pulses, 1K-trigger 7, three-phase sensor 14 of the output current of the inverter and the inputs of the elements 2I- NOT 15-26 and ZI 27-32 are made

tirovaniye of electric drives, advantageously, that at the exits of elements

This is true in those cases where the power factor of the load is cos (is variable.

The purpose of the invention is to improve the energy performance of the converting phrases cF and cF,

2I-NOT 15 and 16, for example, the first and second channels of a logical node form sequences and owls, defined respectively

by eliminating counter-switching switches of the inverter rack keys and reducing the control signal to the minimum necessary power.

Fig. 1 shows a DC converter in a quasi-sinusoidal voltage; Fig. 2 shows timing diagrams explaining the principle of operation of the converter.

The device for controlling three-phase-25 libiM bridge inverter 1 contains a master oscillator 2, to the output of which two dividers 3 and 4 frequencies are connected, through element 2 OR 5 connected to a counting input, and through element 2I-NOT 6 - to the installation 1 -Input 1K-trigger 7, to the K-input of which a logical unit is fed (for example: measures connected to the positive power bus). The output of element 2И-НЕ 6 is also connected to the input of a three-channel distributor 8 pulses, made according to a scaling circuit, for example, on three 1K-flip-flops 9.- 11. Outputs

the outputs of logic elements 2I-NOT 21 and 22 - a sequence of pulses

(cF) a and cFa, and at the outputs of the logic elements ZI 27 and 28 - the sequence of pulses cFacFId and cFacFI ,,.

Other channels of logic node 12 are similarly executed, at the remaining outputs of which form a sequence of pulses, defined by the following logical expressions: at the output of the ZI 29 aCaAR element, the ZI 30 element - aF baFIg, element-) FIc, the ZI element 32 - "Fcbf" Output logic node

WITH

12 is switched on the amplifier-decoupling unit 13, which provides the necessary. Maximum matching of the output stages of the control unit and the input stages of the three-phase bridge inverter 1

converter

I

Three-phase sensor 14 polarity. the distributor 8 pulses and 1K-trig-40 of the output block of the inverter can have a power 7 connected to the inputs of the logical versions. On

35

node 12, the outputs of which are through the amplifier-uncoupling node 13. connected to the control inputs of the keys of the three-phase bridge inverter 1. The three-phase sensor 14 of the polarity of the output current of the inverter with the direct and inverse outputs is connected to the output pins of the latter.

Each of the six channels of the logical node 12 contains the series-connected elements 2И-НЕ 15-20 (the inputs of which form the inputs of the logical node 12), the elements 2И-НЕ 21-26, the free inputs of which are connected to the corresponding inputs of one of the elements 2И-НЕ 15- 20, and ZI elements 27-32, two inputs of which are connected to BE paths of elements 2I – 15–15 between the outputs of the distributor 8 pulses, 1K flip-flop 7, three-phase sensor 14 of the output current of the inverter and the inputs of elements 2I – NO 15 26 and ZI 27-32 are made as follows.

in terms of cF and cF,

2I-NOT 15 and 16, for example, the first and second channels of the logical node 12 form a sequence of pulses, defined respectively

the outputs of logic elements 2I-NOT 21 and 22 - a sequence of pulses

(cF) a and cFa, and at the outputs of the logic elements ZI 27 and 28 - the sequence of pulses cFacFId and cFacFI ,,.

Other channels of logic node 12 are similarly executed, at the remaining outputs of which form pulse sequences defined by the following logical expressions: at the output of element ZI 29 of Fig. 1, for example, it is made according to the circuit of current transformers 33-35, secondary windings which are connected to the circuit of the amplifier-formers 36–38 pulses, the functional characteristic of which is the conversion of a quasi-sinusoidal signal (the output current of the converter operating on a reactive load) into a unipolar normalized in 0-1 minutes signal code (e.g., a power amplifier, a comparator or a Schmitt trigger) outputs shaping amplifiers 36

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38 pulses form the direct output of sensor 1 (6.0) also connected to inverters 39-41, the output of which 1.1 emit the inverse output of the sensor LS).

taking into account the existing element base of the microcircuit, for example, cepi-M 155, 133 or 134 elements, realizing the function of the elements ZI-27-32, it is advisable to perform in the form of series-connected elements ZI-NO 42-47 and HE 48-53, as shown in FIG. .one.

The principle of operation of the converter is explained by the time diagrams shown in Fig. 2, where u is denoted, g is the output phase voltage.

three-phase bridge inverter i,. h t

 ,, is the main harmonic of the output phase current for different values of the power factor of the converter load (coscf О, cos tp Ц 0.8.67 - lagging, cos cos ц

, 867 - leading), 1 ,,, l

 W A J

, 4d are the output signals of the three-phase sensor 14 of the polarity of the output current of the inverter (phase A) for the respective values of co ((Ug are the pulses at the output of the master oscillator 2, and u are the pulses from the outputs of divider 3 and 4 frequencies).

After the logical summing operation, the output of element 2IL 5 forms a sequence of pulses, and after the operation of logical multiplication and inversion, a sequence of pulses IL (at the output of element 2И-НЕ 6), according to which the state of the 1K-trigger 7 and the distributor is determined 8 pulses. At the outputs of the 1K-flip-flops 9-11, there are direct and inverse sequences of pulses (j and -U (,. With a shift between them).

are

At the K-output of the 1K flip-flop 7, form a sequence of modulated

by pulse duration F - U. Sequences of pulses are respectively indicated and at the outputs of elements 2I-NOT 15-26 U, - U2g and elements ZI 27-32 and, - at the outputs of the latter, form the signals defined by the above logical controls, which, after amplification and the necessary galvanic isolation the amplifier-decoupling unit 3 is fed to the control inputs of the three-phase bridge inverter 1. In accordance with the operation algorithm, a voltage with PWM is formed at the output of the converter (, Fig.2). Thus, the proposed converter compared with the known

8055

It forms an input voltage that is not distorted by the load response with the lowest POWER control provided by limiting the duration of the control signals of the keys of the three-phase bridge inverter 1. In this case, it is possible to completely eliminate the counter-switching of its keys, which is especially important for transistor variants of the power part of the converter ( and, as a result, eliminate the possibility of the occurrence of through 15 currents), as well as reduce the total number

ten

0 25 „

0 5

0

commutation.

Claims (1)

Invention Formula Device for controlling a constant-voltage quasi-sinusoidal converter with a PMM, containing a master oscillator, to the output of which two frequency dividers are connected, via element 2IL or connected to the counting input and element 2IN-NOT to the installation 1 input of the IK trigger and three-channel distributor impulses made according to a scaling circuit with direct and inverse outputs a, a, b, b, c, c, with its input connected to the output of element 2I-NOT, and outputs to the inputs of a logical node made in the form of six channels, each which includes two 2I-NOT elements, and the connections between their inputs and outputs with the F output of the 1K flip-flop and the output of the pulse distributor are determined by the logical expressions cFa, bFc, aH, cFa bFc, iFb, cF, bF, respectively, aF, cF, bf, aF, o t 5 0 five and that, in order to improve the energy performance of the converter during operation its load with varying to the lagging and leading load angle, it is equipped with a three-phase polarity sensor of the inverter output current with direct and inverse outputs 1e () -L (b, c) and each channel of the logical node is equipped with logical elements1 -1i, which perform the function of the ZI, and the connections between its inputs, the outputs of elements 2I-NOT and the three-phase sensor of the output current of the inverter are determined for the six logical channels of the logical node, respectively. 21n aPTjaFI 65 aFbaFI eight I I INI I II Ml II I II Hill mini I III a I. 4e ii-, 13.} -Innn pll r-innji nr-tn n nrLrui .. mjajinr. nJiflOJLana-tuannrzrrr ::: i GSPL. YY ") .). | ) Compiled by O. Parfenova CLTUL FIG. g t T t  7 Editor P.Geershi Tehred M.Didyk Order 6006/55 Circulation 659Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader L. Pilipenko