SU1511833A1 - Device for controlling d.c. to quasisine a.c. voltage converter - Google Patents

Description

The invention relates to a conversion technique and can be!> Used to build secondary power supplies for electric automation devices and AC electric drives with mana power (up to kVA units), operating both with variable and constant load, in cases where coordination of voltage levels is required the supply network and the consumer, the improved quality of the converted electric energy and acceptable weight and size characteristics of the secondary source.

The purpose of the invention is the provision of regulation of the magnitude of the output voltage.

In FIG. 1 is a timing chart explaining the formation of the output voltage of the proposed Converter (a), and the structural diagram of its power unit (b); in FIG. 2 is a generalized block diagram of the control unit of the proposed converter (a), a block diagram of one of the embodiments of the power section of the converter with intermediate-high-frequency conversion (b), the dependence of the magnitude of the first harmonic of the output voltage of the converter and the harmonic coefficient of the output voltage K _r (u) on the duration adjustment pause sat (c); in FIG. 3 is a block diagram of a converter control unit with L = 6; in FIG. 4 is a timing diagram explaining the formation of the control signals of the keys of the inverter cells and the output voltages of the inverter cells.

The device (Fig. 16) contains L single-phase bridge inverter cells 1.1-1.L with galvanically isolated from outputs connected in series. Keys 2-5 of each inverter 30 cell form its first (keys 2 and 3) and second (keys 4 and 5) racks.

The control unit 6 (Fig. 2a) with the keys of the inverter cells 1.1-1.L co35 holds the master oscillator 7, connected to the first input of the main 2-channel 8-pulse distributor, to the input of the main frequency divider 9, to the first input of the first additional 40 L- channel distributor of 10 pulses to the inputs of the first additional frequency divider 11 and phase shifting unit 12. The output of the main frequency divider 9 is connected to the second input of the main pulse distributor 8, the output of the first additional frequency divider 11 is to the second input ervogo ed additional distributor 10 pulses, and the output of the phase shifter assembly 12 - to the first input of the second additional pulse distributor 13 and to the input of the second additional frequency divider 14, the output connected to the second input 13 of the pulse valve. Each of the distributors 8, 10 and 13 pulses can be performed according to the scheme of the shift register in series

connected JK- or D-type triggers galvanically decoupled sources with combined counting inputs (except for the first trigger). In this case, the counting input of the first trigger forms the second input of the pulse distributor, the first input of which is formed by the counting inputs of the remaining triggers. The paraphase outputs of each of the channels of the distributors 8, 10 and 13 pulses are connected to the corresponding inputs of the logical nodes, the outputs of which are connected to the control inputs of the K-x keys of the inverter cells 1.1-1.L. Each of the logical nodes 15.1-15.L is made on two logical elements 2I 16 and 17, two logical elements ЗИ 18 and 19, two logical elements NOT 20 and 21 and one logical element 2 OR 22. Constructive execution of i-ro logical node (from the number of the indicated L nodes 15.1-15.L) and its connection with the distributors * 8, 10 and 13 and with the keys of the 2-5th inverter cell (from the number of L inverter cells 1.1-1.L), where i- 1-L are defined by the following logical expressions:

g r

V; = V, <ή = where О '· -Ср ¹ * are determined by logical expressions (1);

key management signals 2-5 of the inverter cell l.i.

The main 9 and additional 11 and 14 frequency dividers are performed with division factors of 3L and L / n, respectively.

Inverter cells in the proposed converter have galvanically isolated outputs. In the circuit of FIG. 16, galvanic isolation is carried out by performing inverter cells with a transformer output. In this case, the output transformer cells operate at the output frequency of the converter and in cases where it is necessary to obtain a low frequency (tens of Hz) at the output, they have large dimensions and weight. Therefore, in the region of low output frequencies, it is advisable to galvanically decouple the outputs of these inverter cells by providing the latter with DC voltage. An example implementation of such a converter 5 is shown in FIG. 2b. The galvanically isolated power sources of the bridge inverter cells are DC / DC converters of a different level, performed according to the zero-point scheme and operating at an intermediate high frequency. Transistors connected on the secondary side parallel to the rectifier diodes provide the flow of reactive load current.

To simplify the implementation, transistors can be controlled without monitoring the current in the power circuit of the output inverters by directly using intermediate high frequency signals. , I,. to

Ψηβ4 ’HDTV *

In the proposed converter, the input of the main frequency divider 9 can be connected not to the output of the master oscillator 7, but to the output of the first additional frequency divider 11. In this case, the division coefficient of the main frequency divider 9 is selected to be equal to Zn. 3.

The principle of operation of the proposed Converter for L = 6 is illustrated by the timing diagrams in FIGS. 1a and 4, where the following notation is used: u ₂ ^_U 2 ~ the voltage at the outputs of the inverter cells 1.1-1.6; u ₂₂ , and ₂₂ ~ the curves of the output quasi-sinusoidal voltage of the converter, respectively, at 4 * = 0 and U- * = 1/6; and _eg is the signal at the output of the master oscillator 7.

Consider the operation of the proposed Converter.

The master oscillator 7 (Fig. 3) form a sequence of clock pulses of frequency 6Lfg = 36f (u _3r in Fig. 4), where f ₂ is the frequency of the output voltage of the Converter. From the output of the master oscillator, the pulses are fed to the first inputs of the main 8 and the first additional 10 pulse distributors and to the inputs of the main frequency divider 9, the first additional frequency divider 1I and phase-shifting unit 12. From the output of the main frequency divider 2f ^

1511833 (the resulting coefficient of dividers 9 and 11 is 3L = 18) are fed to the second input of the 8 pulse distributor, at the outputs of which 2L = 12 pairs of square-wave rectangular signals of frequency f are shifted relative to each other for one clock frequency period, which is 7 /31.= 7/18 (the period of the output voltage is 27). The second input of the pulse distributor 10 receives 6nf ₂ frequency pulses from the output of the frequency divider 11, while at the outputs of the indicated distributor L = 6 pairs of rectangular phase-frequency signals of the frequency 3nf ₂ are shifted relative to each other by 7/3 = 7/18. From the output of the phase-shifting unit 12, the frequency pulses 6Lf ₂ = 36f ₂ , shifted relative to the clock pulses by an interval ¢ 4 adjustable in duration, go to the first input of the pulse distributor 13 and to the input of the frequency divider 14, from the output of which 6nf ₂ frequency pulses go to the second input distributor 13. At the outputs of the specified distributor 'form L = 6 pairs of paraphase rectangular signals of frequency 3nf ₂ , shifted relative to each other by 7 / 3L = 7 / I8. The signals from the outputs of the distributors 8, 10 and 13 are fed to the corresponding inputs of the logical nodes 15.1-13.6, in which the control signals of the inverter cells are generated in accordance with formulas (1). In the timing diagrams of FIG. 4, key management signals are shown only for inverter cells 1.1 and 1.2, and the key management signals of the remaining inverter cells have the same shape, while the control signal systems are shifted relative to each other by 7/31, = 7/13. Switching the keys of the inverter cells in accordance with the control signals received at their control inputs ensures the formation of voltages u ₂ ~ u ₂ (Fig. 1a) at the outputs of the inverter cells sequentially shifted by 7 / 3L = 7/18. By summing these voltages in a common circuit formed by the series-connected outputs of the inverter cells, output quasi-sinusoidal voltages of both _2X and _2d are obtained (at ° C * = 0 and 4 * = 1/6, respectively, Fig. 1a).

Regulation of the output voltage in the converter is carried out by the method of partial pulse-width pulse regulation most effective from the point of view of distortion: during regulation, deep voltage dips to zero appear only in the region of minimum voltage values, and the later, the greater the number of cells L (Fig. 2c). From the graphs ^u 2 _& = f (<k *) and K _r (u) = f (oi *) in FIG. 2c, it can be seen that, for L = 6, for example, in the control range, the values of the fundamental harmonic are 1.06-0.5 = υ _{2Σ1, the} distortions do not exceed 25%.

The invention allows to expand the scope of the device by expanding its functionality. In addition, the implementation of the device without regulated power sources (due to voltage regulation according to a certain al ..

. algorithm directly in the inverter cells) can significantly reduce (by about 10%) the resulting losses in the device and, accordingly, improve overall dimensions.

^{1 The} possibility of 100% regulation of the output voltage allows without additional funds on the power circuit to protect the converter from overcurrents.

I

Claims (3)

Claim 1;, 1;, ..., 1 ^, 1 _b in each channel, respectively, as well as similarly executed logic nodes, connected by inputs to the corresponding outputs of the corresponding distributors, and outputs designed to connect to the control inputs of the corresponding keys of the corresponding inverter cells, and the inputs of the first additional distributor are connected to the output of the master oscillator directly and through the first additional frequency divider, the inputs of the second additional distributor are connected to the wide pazonnogo phase shifting unit directly and via a second additional frequency divider input phase shifting unit connected to the output of the master oscillator and ί-th logic from among the L said nodes, its connection with the valves pulses and with keys i-th inverter cell defined by the following logical expressions: Y; = P; Ρ ^ ίπςΐ; + m · 1; ) - for the first key rack, connected to the first bus-r pi11 ^Thaniah »ψ; = V; - for the key of the first rack connected to the second bus ping _ _ _ _ ^tan ia; ψ · -R) - for the key of the second rack connected to the first bus pi, _ tania; ,, ιν - IG ψ; = ψ · - for the key of the second rack connected to the second power bus; where i = l-L. 1. A device for controlling a DC-DC converter to a quasi-sinusoidal variable, including L bridge inverter cells with galvanically isolated and connected in series outputs, the keys of each inverter cell forming its first and second racks, one end connected to the first power bus of the converter, and the other end - to the second bus containing the master oscillator, the output connected to the input of the main frequency divider, the main 21 _.- channel pulse distributor with a paraphase э · '> ··· ® outputs of each channel, inputs connected to the outputs of the master oscillator and the main divider and providing voltage generation at the outputs of these cells with a pause of 7/3 between half-waves and a sequential phase shift by an angle of «« / 3L between half-waves and consecutive phase shift by an angle of 7 / 3L between cell voltages, characterized in that, in order to control the magnitude of the output voltage, it is equipped with a wide-range phase-shifting unit, two additional frequency dividers by L / n, where η is the number of them pulses in the interval 5g / 3 of the output voltage, two additional L-channel pulse distributors with paraphase outputs pc, 111 (, ..., 111 ^, 111 ^, .., 111 ^, 111- and 2. The device according to π. 1, characterized in that. with direct connection of the main frequency divider with the output of the master oscillator, it is made with a division coefficient equal to 3L. 3 "The device according to claim 2, characterized in that, for the sake of simplification, the input of the main frequency divider is connected to the output of the master oscillator through the first additional frequency divider and is made with a division coefficient дел equal to Зп. a <.ub FIG. 2. FIG. 4