SU1229929A1 - Device for controlling three-phase bridge inverter - Google Patents

Abstract

The invention relates to converter equipment and may be used. when building control systems for three-phase inverters designed for frequency-controlled electric drives. The purpose of the invention is to provide control of the output voltage. An example of the implementation of the formation of an output voltage of an improved form based on logic elements is given. The internal connections between elements of a control logic node are determined by logical expressions that can be transformed. The device makes it possible to improve the energy performance of the electric drive as a whole, especially in start-up modes, by providing a frequency start with a corresponding decrease in the supply voltage of the engine. 2 Il. ьсю со со 1чЭ со

Description

The invention relates to converter equipment and can be used in the construction of control systems for three-phase inverters designed for frequency-controlled electric drives, as well as in the construction of autonomous centralized power supply systems.

The purpose of the invention is to provide control of the output voltage.

FIG. 1 shows a schematic diagram of a device for controlling a three-phase bridge inverter; in fig. 2 shows timing diagrams explaining the principle of operation of the device and the formation of the phase voltage of the inverter controlled from it.

A device for controlling a three-phase bridge inverter (Fig. 1) contains a setting generator 1, in general, pej is frequency-guided and synchronizes operation of the device. The output of the master oscillator 1 is connected to two dividers 2 and 3 frequencies, to the outputs of which are connected element 2ILI 4, element 2И– NOT 5, as well as a pulse width modulator 6 connected to the output of frequency divider 2. The output of element 4 is connected to the counting input of the I-K-flip-flop 7, to the setting input Y of which the output of the element 5 is connected, and logical input is fed to the input K. In this case, the input K can either be left free or connected to the positive terminal of the power supply unit.

The output of the element 5 is also connected to the input of the distributor 8, which contains three Y-K-flip-flops 9-11, the outputs of which form the forward and inverse outputs of the distributor 8-a, a; in, in; c, c, and are connected to the inputs of a six-channel logical node 12. The other inputs of logical node 12 are connected to the output of modulator 6 and the output of element 2IL 13, the inputs of which are connected to the output of trigger 7 and modulator 6. Internal links between elements of logical node 12 are defined by the following logical expressions:

aVbFaVc (FaVQ) Vac (FaVQ); aVbFaVc

(F; vQ) Vac (); bVcFaVa (FaV Q) Va5 (FaVC5);

b VcFaVa (F ,, VQ) Vab (F "VQ);

cVaFo.Vb (FaVQ) Vbc (F V VQ);

cVaFaV 5 (F.VQ) Vbc (F, VQ).

It should be noted that the logical expressions defining the connections between the elements of the logical node 12 can be transformed. Accordingly, the internal structure of the logical node 12 may be different. FIG. 1 shows a variant of the logical node 12, each of the channels of which contains serially connected elements ZI-NO 14-19, elements ZI-NO 20-25 and elements 2I-NOT 26-31, to the second input of which are connected the outputs of the corresponding elements 14-19 of adjacent channel of logic node 12, to the second input of elements 20-25 are connected the outputs of the corresponding elements 2И-НЕ 32-37, the inputs of which are connected to the output of the modulator b and the corresponding output of the distributor 8. Communication between the outputs of the distributor 8, element 13 and the inputs of the elements 14-19 are made as follows way that the outlet, for example, logical Elemental cient 14 lervom channel logic unit 12 generates pulses, characterized by a logical expression ac (FaVQi). and at the output of element 15 in the second channel ac () - At the output of elements 32 and 33 of the same channels, impulses are defined, determined by logical

expressions bF and bFg, and at the output of elements 20, 21 - a ac (FaVQi) bFa. At the output of the device, i.e. at outputs 26 and 27, they generate pulses defined by the following expressions:

ac () b aa ac (FaVC),

five

0

i5 (FaVQ) bFaaac (FaVQ) are equivalent expressions approved above.

The connections between the logic elements in the remaining channels of the logical node 12 are similarly executed, the outputs of which form sequences of control pulses.

The principle of operation of the device for controlling a three-phase bridge inverter is explained in timing diagrams in FIG. 2, where the following symbols are taken: Ui is the signal from the output of generator 1; UaUa - pulses from the outputs of frequency dividers 2 and 3.

To form a symmetric inverter output voltage curve, the division factors NI and Na of the divider 2 and 3 should be c1 related by the ratio Ni N 2 J; 1. The greater the value of NI and N2, the better the quality of the output electricity 5 (the lower the current harmonic coefficient), however, the dynamic losses in the inverter increase. The optimal value of NI and N2 is 4-8 (NI 5 is adopted in Fig. 2). After the logical summation operation is performed, the signal U4 U2 H-Ua from the output of element 4 is fed to the counting input of trigger 7. The device under consideration allows the keystone modulation of UBUX to be realized. An optimum ratio of the upper and lower bases of the approximated trmappea (modulation law) 2: 3 is obtained for the three-phase invertors by the magnitude of the amplitude of the main harmonic and the harmonic ratio of the output voltage. It also allows you to use common signal Q to form control signals in all six channels of logical node 12. The sequence of signals Q at the output of trigger 7 is obtained using the principle of quasi-single-band modulation, which is based on the comparison of different-frequency signals and the selection of the difference frequency signal . To automatically set the trigger 7 to the initial state (Q 1), every 1/6 of the period of the output frequency feux, the 1 input of the trigger 7 gives a signal Us О from the output of element 5, and to the input K a logical unit. In accordance with the known table of states of the 1K-flip-flop, the sequence of signals Q in this case becomes unambiguous. The signal frequency Q is modulated according to the simplest linear triangular law and is equal to 6feb.x. The LJ5 signal is also fed to the input of a three-channel distributor 8, the outputs of which have a sequence of three-phase direct and inverse pulses a, b, with a frequency fnux synchronized with the signal Q.

Voltage regulation in a three-phase bridge inverter is dried, either at one of the internal frequencies of the Q signal generation (in Fig. 2, at the frequency of the U2 signal) or multiplied by it, or at the independent frequency. The signal Fa from the output of the modulator 6, whose duration and is proportional to the control signal, logically adds to the signal Q element 13 and the resulting signal Uis is fed to the input of logical node 12. After the corresponding logic operations are performed on the pulse sequences at the outputs of the elements 14 and 15 there are pulses UM, Uie-; at the output of element 32, U32 pulses; at the output of element 20, a sequence of U20 pulses. At the outputs of the device formed by the outputs of elements 26-31, there are sequences of control pulses U26-Usi. In accordance with these signals on the intervals of conduction - zt - l

6 6 and 5 - 7 switch the beak

These are frequency controlled, based on asynchronous and synchronous motors. In this case, various drive laws can be implemented. When the modulator 6 is performed according to the one-vibrator circuit in a three-phase inverter, the law U / f const is per formed.

Thus, the device provides an important function — control of the output voltage. Its use makes it possible to significantly extend the range of use of a three-phase inverter controlled from this device, to improve the energy performance of the electric drive as a whole, especially in start-up modes, by providing a frequency start with a corresponding decrease in the motor supply voltage.

20

35

40

Claims (1)

Invention Formula A device for controlling a three-phase bridge inverter, comprising a master oscillator, the outputs of which are connected to the inputs of two frequency dividers, outputs  which are connected through the first element 2 OR to the counting input and through the element 2I-NOT to the 1-input of the 1-K-flip-flop and the input of the three-channel pulse distributor, made according to the recalculation scheme on three OQ 1-K-triggers, the direct and inverse outputs of which are a, a; b, b; The c, c are connected to the first inputs of the logical node, the second input of jcoToporo is connected to the inverse output of the Q 1-K flip-flop, and the outputs of the logical node are outputs of the device, characterized in that, in order to control the output voltage, it is provided the second element 2 OR and the pulse width modulator, the input of which is connected to the output of the first of the frequency dividers, the output F of the unit is connected to the third input of the logical node and the input of the second element 2 OR, the second input of which is connected to the inverse input 1-K- trigger and in output (FaVQ) - to the fourth input of the logical node, and the following logical expressions: aVbE, Vc (F VQ) Vac (FaVQ); 50 aVbFaVc (F «VQ) Vac (EaVQ); whose inverter according to the linear PWM law of the 45 P logical node is determined by the following (. p. di. 11T 1HF / H111) SL1 OLI TIO 1L C1BA IX Taking into account the adjusting pulses F ,,) in accordance with a specific fragment (period) of the signal Uia, and on the conduction interval l - 5 - by the signal with post-T 6 This duration of the adjustment pauses is a fragment of the signal Fa. After amplification and the necessary galvanic isolation, the signals Uae-Usi are fed to the control inputs of the three-phase MOSTY inverter, the output voltage of which (phase) is shown in FIG. 2 The most appropriate area of application of the device is a precision AC drive, in particular bVcF, Va (FaVQ) Vab (EaV); 55 bVcFaV (FaVQ) Vab (F, VQ); cVaF.vb (F v v Q) V bc (FaVQ); cVaFaV b (FaVQ) Vbc (FaVQ), frequency controlled, based on asynchronous and synchronous motors. In this case, various drive laws can be implemented. When the modulator 6 is executed according to the one-oscillator circuit in a three-phase inverter, the U / f const law is implemented. Thus, the device allows for an important function — control of the output voltage. Its use makes it possible to significantly extend the range of use of a three-phase inverter controlled from this device, to improve the energy performance of the electric drive as a whole, especially in start-up modes, by providing a frequency start with a corresponding decrease in the motor supply voltage. 20 Invention Formula 0 A device for controlling a three-phase bridge inverter, comprising a master oscillator, the outputs of which are connected to the inputs of two frequency dividers, outputs  which are connected through the first element 2 OR to the counting input and through the element 2I-NOT to the 1-input of the 1-K-flip-flop and the input of the three-channel pulse distributor, made according to the recalculation scheme on three Q 1-K-flip-flops, direct and inverse outputs of which are a, a; b, b; The c, c are connected to the first inputs of the logical node, the second input of jcoToporo is connected to the inverse output of the Q 1-K flip-flop, and the outputs of the logical node are outputs of the device, characterized in that, in order to control the output voltage, it is provided the second element 2 OR and the pulse width modulator, the input of which is connected to the output of the first of the frequency dividers, the output F of the unit is connected to the third input of the logical node and the input of the second element 2 OR, the second input of which is connected to the inverse input 1-K- trigger and in stroke (FaVQ) - a fourth input logic node, and strukschimi logical expression E: P logical node is determined by pti di. 11T 1SH / G111) S1L OLI TIO 1L S1АЯ IX aVbE, Vc (F VQ) Vac (FaVQ); 50 aVbFaVc (F «VQ) Vac (EaVQ); bVcF, Va (FaVQ) Vab (EaV); 55 bVcFaV (FaVQ) Vab (F, VQ); cVaF.vb (F v v Q) V bc (FaVQ); cVaFaV b (FaVQ) Vbc (FaVQ)