SU1121757A1 - Voltage converter - Google Patents

Abstract

1. A VOLTAGE CONVERTER containing an output power stage with two groups of transistors, each of which consists of four series-connected transistors, parallel to each of which diodes are connected, two capacitors, the first plates of which are connected to the corresponding input pins of the output stage, and the second through recuperating diodes connected to the junction points of the upper and lower pairs in each group, respectively, and the junction points of each pair of transistors form the output the single outputs of the power stage, while the bases of the transistors are connected to the outputs of the control node, which differs so that, in order to reduce the installation power of the converter, by providing two independent; adjustable output voltages with one power output helmet: yes, an integrated pulse-width modulator, a first and a second series resonant LC circuit, connected in parallel to the output terminals of the power stage, with output transformers with output rectifiers and filters connected in parallel with capacitors In this way, the inputs of the control unit are connected to the outputs of the integrated pulse-width modulator. 2. A converter according to claim 1, characterized in that the integral pulse-width modulator contains a sinusoidal signal generator node consisting of a square-wave pulse generator connected to the first sinusoidal driver, the node’s first output cable and the frequency divider input (L From the output of which is connected to the Blorp-i output of the node and the input of the second shaper of a sinusoidal signal, and the outputs are forcing; the formers form the third and fourth c) node inputs that are connected through two controllers to Ode the first node of the comparison and the first two inputs of the driver control pulses, the third and fourth inputs of which are connected respectively to the second and first outputs of the node of the sinusoidal signal generator, the fifth input to the output of the clock and multiplier, the sixth and seventh to the first and third outputs of the first node compared, the eighth to the output of the second comparison node, the inputs of which are connected to the first and third outputs of the first comparison node, the outputs of the control pulse driver are connected to the inputs of the latitude o- fflylcnogo modulator, the outputs of which form the output terminals of the modulator.

Description

The invention relates to converter equipment and can be used in the development of secondary power sources, in particular plasma ion sources. A voltage converter is known that contains capacitors connected in series, parallel to each of which is connected the connection of the primary winding of the transformer with a switching transistor, forming at least two half-bridge converters that work on the same common core.  The disadvantages of such a voltage converter are reduced efficiency due to the lack of energy recovery of the transformer inductance of the transformer, as well as the presence of only one controlled output.  A voltage converter is known that contains a chain of four transistors connected in series to the output transformer 2.  The disadvantages of this voltage converter are reduced efficiency when operating on a reactive load, as well as the presence of only one controlled output.  The closest technical. The essence of the invention is a voltage converter, which contains an output stage with two. groups of transistors, each of which contains four series-connected transistors, paral | For each of which diodes are connected, two capacitors a, o of one of the plates of which are connected to each other; The 4 input pins of the output stage and the others through the recovery diodes are connected to the connection points of the upper and lower pairs of transistors in each group, the connection points of each pair of transistors in the group form the output pins of the power stage, and the bases of transistors (W.  The drawback of the device is the possibility of providing only one adjustable output voltage channel with one power stage. The purpose of the invention is to reduce the converter power by providing two independent adjustable output voltage channels with one power output stage.  I The goal is achieved by the fact that a voltage converter contains an output power stage with two sets of transistors, each of which consists of 1 three consecutively connected transistors, parallel to each of which are connected diodes, two capacitors, one of the plates of which are connected to the corresponding input pins of the output stage, and the others are connected via recuperating diodes to the connection points of the respective upper and lower pairs in each group, with Each pair of transistors forms the output terminals of a power stage, with the base of transistors connected to the outputs of the control unit, an integrated pulse-width modulator is introduced, the first and second series resonant LC circuit connected in parallel to the output terminals of the power stage, parallel to the capacitors of which the output transformers with output slots and filters, while the inputs of the control node are connected to the outputs of the integrated pulse-width modulator.  At the same time, the integral pulse-width modulator contains a generator of sinusoidal signals consisting of a square pulse generator connected to the first driver of sinusoidal signals, inputs of the frequency divider and first outputs of the node, the output of the frequency divider connected to the second output of the node and input of the second sinusoidal generator the signal, the outputs of these drivers form the third and fourth outputs of the node, which are connected via two controllers to the inputs of the first comparison node and the first two inputs The control pulse generator, the third and fourth inputs of which are connected to the second and first outputs of the sinusoidal signal generator node, the fifth input to the output of the clock generator, the sixth and seventh to the first and third outputs of the first comparison node, the eighth to the output of the second comparison node, the inputs of which are connected to the first and third outputs of the first comparison node, and the outputs of the control pulse shaper are connected to the inputs.  pulse width modulator, the outputs of which form the output, the outputs of the modulator.  FIG.  Figure 1 shows the voltage converter; FIG. 2 is a block diagram of the integrated pulse width modulator J in FIG.  3 and 4 are diagrams of the modulator operation; FIG.  5 shows the control circuit in FIG.  6 - diagrams of control circuit operation.  Voltage converter (FIG. 1 consists of an output stage 1 assembled according to a bridge circuit with recuperating circuits, containing eight power transistors, twelve diodes and a capacitive divider, control circuits 2 containing impulse amplifiers providing amplification and shaping the signal arriving at its input, integral width pulse modulator 3, the first 4 and second 5 series resonant circuit, the first 6 and second 7 transformers, the first 8 and second 9 rectifiers, the first 10 and second 11 filters, the first 12 and second 13 loads, and the output of the modulator 3 is connected to the input of the control circuit 12, the outputs of which are connected to the transistors of the output stage 1, the output of which is connected to the inputs of the first 4 and second 5 series resonant circuit, the outputs of which are connected to the first 6 and second 7 transformers, first 8 and the second 9 rectifier mn, the first 10 and the second 11 filters, the first 12 and the second 13 load.  The integral pulse width modulator 3 (FIG.  2) consists of a generator of 14 sinusoidal signals, containing a generator of 15 rectangular pulses, a first sinusoidal signal shaper 16, a frequency divider 17, a second shaper 18 of a sinusoidal signal, and a clock generator of the first 20 and second 21 regulators of a forma 22 containing a totalizer 23 ampli -tour detector 24, switch 25, first comparison circuit 26 containing rectifier 27 with filter 28, comparator 29, second comparison circuit 30 containing adder 31, inverting 1 1 1st amplifier 32, impulse forcing device 33 Bs containing a latitude and a ffly modulator.  The control unit 2 (FIG.  5) consists of a push-pull power amplifier 34, a pulse transformer 35, eight pulse amplifiers 36, the pulse amplifier 36 consists of an amplitude detector 37, a delay shaper 38, an output stage 39, a rectifier 40, a shaper 41, and the output of the push-pull power amplifier 34 is connected with the primary winding of the pulse transformer 35, and eight secondary windings of the transformer 35 are connected to the inputs of eight corresponding and powerful amplifiers 36, and the output of the amplitude detector 37 is connected to the input of the form ovatel delay 38, whose output is connected to the input of the output stage, the output of shaper 41 is connected to the input of the amplifier 42, the input of rectifier 40 is connected to the input of the amplitude detector 37 and the output is connected to. one of the inputs of the output stage 39.  Converter converter works as follows.  The generator 15 rectangular pulses and generates pulses of rectangular shape with a frequency J, the output of which is connected to the input of the divider 17 frequency (which is possible at a frequency ratio of 1/2 to use a countable tripod) and the input forimage 16 of a sinusoidal signal (for which it is possible to use a resonant circuit or bandpass filter).  The output of the frequency divider 17 is connected to the input of the driver 5 siausoidalyyo signal, while the outputs of the generator 14 are. lecTo the following signals: output 14.3 and 14.4 - sinusoidal signals of equal amplitude with frequency Fj and F, respectively: output 14.1 14, 2 - rectangular pulses with frequency F and F, respectively.  Sinusoidal signals from outputs 3 and 14.4 are fed to inputs 20.1 and 21.1 of the controllers 20 and 21, outputs 20. 2 and 21. 2 of which are connected to the inputs 22.1 and 22.2 of the former 22.  Inputs 22.1 and 22. 2, the former 22 is connected to the inputs of the adder 23, the output of which is connected to the input of the amplitude detector 24 at the output of which a modulating part is obtained, which is obtained by adding two frequencies in the adder 23.  From exit 22. 9 shaper 22 signal is received.  at the entrance 33. 1 shaper 33 and ipl and respectively to the control input of the pulse-width modulator ZZ (PWM).  Entrance 33 2 shapers 33 pulses, and through it the clock pulses from the output go to the clock input of the PWM. 22 10 shaper, t. e.  with the outputs, the switch 25, and the input 33. 3 formers of 33 pulses, and, consequently, impulses from the output 22 also arrive at the PWM distribution input. 11 formers 22 ,.  t. e.  from the output of the Vj switch 25.  The phase outputs of the PWM are connected to the inputs 33. 4 and 33. five.  Clock pulses from output 22.  10 and 22. 11 "driver 22 and, Respectively, from the output Y, and 2 switches 25 are sequences of pulses arriving at the outputs 22. 3, 22,4,22. 5 generator or, which is the same, to the inputs X,, Xg of the switch 25, for which you can use a standard switch of type K155KP7.  At the entrances 22. 6, 22. 7, 22. 8 driver 22 and respectively to the inputs X, X, -, Xg.  the switch 25 receives signals from the outputs of the comparison circuits 26 and 30.  At the entrances 26. 1 and 26. 2, the comparison circuit 26 receives the sinusoidal signal from the decoding codes 20. 2 and 21. 2 regulators 20 and 21.  These signals are exported, filtered by rectifier 27 and filter 28, and fed to the input of comparator 29, which compares the signal sigals, if the signal from the output of the rectifier and filter 27 is greater than the signal from the output of the rectifier and ftutra 28,. then at the output of the comparator 29 and, respectively, at the output 26. 4, circuits 26 compares the WITS signal of a logical unit; if, on the contrary, the signal of a logical zero, V-codes 26. 3 and 26.3, the comparison circuits 26 are connected to the inputs 30. -1 and 30. 2 of the comparison circuit 30, which determines the equality of the signals from the outputs 20. 2 and 21. 2 regulators 20 and 21.  Signal from input 30. 1 enters the non-inverting input of the amplifier 32, the inverting input of which receives a signal from the input 30. 2  In this case, one anode diode. The DOB of the adder 31 is connected to the inverting input of the operational amplifier 32, and the second to the code of the operational amplifier 32, and the cathodes are connected together and connected to the point 30. 3 AOR comparison schemes.  With equal amplitudes of the signals at the output 30. 3, the comparison circuits 30 receive a logical zero signal, and, if they are unequal, a logical one.  This signal is fed to the input 22. eight. driver 22 and, respectively, to the input of the switch 25.  The generator 19 produces pulses with a frequency equal to p P - «F.  At the output of the generator 15 (FIG.  For) there are rectangular pulses with a frequency F, at the output of the frequency divider 17 - pulses with a frequency of 1 Fj (Fig.  Zb), at the output of the formers 16 and 1. 8 sinusoidal signals - the waveform shown in FIG.  Sv and Zg respectively.  Output signals 20. 2 and 21. The 2 controllers 20 and 21 change their amplitude depending on the gain and the controller.  If the amplitude of the signals at the output 20. 2 i 21. 2 are equal, at the output of the adder 23 receive a summed signal of two sinusoidal oscillations with equal amplitudes.  2As; n () l. co6 (il) i / From the hyphenation (1) it is seen that in the signal spectrum there are two frequencies equal to half-sum and half-difference of the main frequencies, t. e.  the frequencies t, F, -F, and F-iy-1-.  The frequency Fj is the carrier, and the frequency F4 is the modulating part.  The frequency is selected with an amplitude detector 24, output 22. 9 shaper 22 appears with a signal frequency FA, which is fed to input 33. 1 puller 33 pulses, t. e.  to the control input of PWM (FIG.  Rear).  In this case, the clock input PWM and, accordingly, the input 33. 2, the pulse driver 33, through the switch 25, receives the clock frequency F from the output of the generator 19, F - “is equal to t (FIG.  Ze).  So F. a.  way, exit 33. 4 and 33.  Forma 71 of the rotator 33 pulses will be a sequence of width-modulated F, + F pulses with a frequency Fj -j-- (FIG.  For), which will go to the entrances of the power stage (Fig.  Zzh and rear).  . The comparison circuit 30 allows only the F frequency of the generator 19 to pass to the switch 25 FJ + F output.  As can be seen from FIG.  2, the inputs X, Xj, Xj of the switch 25 receive signals from the generator 15 ,.  the frequency divider 17, as well as from the generator 19, and to the control inputs X, Xj Xg - signals from the outputs of the rectifier and the filter 27, comparator 29 and 30. 3 comparison schemes 30.  Switch 25.  Works according to the truth table (X is an arbitrary state).  As can be seen from the table, the output of the switch 25 and, respectively, at the input 33. The 2 pulse shapers 33 have clocks with the required frequency depending on the quotient of the outputs 26. 3, 26. 4 and 30. 3 compares 26 and 30.  With equality of both their sig. cash on the outlets 20. 2  and 21. 2 controllers 20 and 21 at exit 30. 3, comparator 30 appears as a logical signal. zero and according to the truth table at the output At the switch 25 on the Wits signal from the output of the generator 19.  These signals are, respectively, a clock and a natm distributor for PWM.  In this case, the control signal for the PWM will be the signal from the output of the amplitude detector 24, the output of the PMM and the output of the pulse maker 33 will be a signal, modulator - F, frequency 8 (FIG.  Rear).  At the output of the power amplifier and, respectively, at the inputs of both circuits, two frequencies equal to Fj which are assigned to circuits 4 and 5 appear on the circuit (Fig.  1) respectively: naturally.  In this case, the power transferred to the load 12 and 13 will be equal to.  If it is necessary to transfer power to circuit 4 (FIG.  1), tuned to the frequency F, the amplitude of the sinusoidal. signal frequency F output 20. 2 regulators 20 are larger than the amplitude of the signal at output 21. 2 regulators 21. 3, t. e.  will cause output 26. 4 comparison circuits 26, at exit 30. 3 circuits 30 comparing tc signals of a logical unit.  In this case, according to the truth table at the outputs Y and yj of the switch 25, the signal from the output of the generator is turned on. 15 frequency F.  This signal will be sent to the clock distribution input PWM (input 33. 2 and 33. 3 shapers 33 pulses).  The modular P1IMM input of the pulse driver 33 receives a signal, the phase and amplitude of which are determined by the formulas j ft-- fA | + Ajt2A, A, Cos (u, - (OjHi I. A, ein (OiitAi5inco, t.  a (j т1-: iг 1 U), i + Wit, provided that the signals have the form P - A, sinoj, t Fj - Aj sintOjt.  When the magnitude of the signal amplitude is larger than the signal F, the magnitude of the amplitude of the resultant signal is determined by a larger amplitude.  At the same time, the modulating frequency is (W, -Wj), t. e.  .  On the modulating - input receives a signal with a frequency of -Fj, T7 - Ch t. e.      Fj, which will provide output PWM and, therefore, the outputs 33. 4, 33. 5 of the driver 33 pulses of a width-modulated signal with a modulation frequency equal to F. (FIG.  4 g, d).  Suppose that most of the power needs to be transmitted to the LC circuit 5, tuned to the FI frequency FJ - -.  In this case, the output 21. 2 controllers 21 amplitude voltage higher than output 20. 2 regulators 20.  This leads to the fact that at the output 26.4 of the comparison circuit 26 there will be a signal with a logic zero level, while at the outputs 26.3 and 30. 3circuits 26 and 30 comparisons, respectively, will be the signal level corresponding to the logical unit.  According to the truth table, these signals, arriving at the inputs of the switch 25, will provide output outputs at the outputs Y and Y equal to the frequencies Fj (FIG.  4a) and PZ (FIG. 45), respectively.  It provides. at the exits 33. 4 and 33. 5 of the pulse generator 33, the signal shown in FIGS. 4e and 4g, respectively.  This signal corresponds to an overmodulated signal of frequencies F and F.  If the signal is equal to zero, the frequency F | according to the truth table at inputs 33.2 and 33. 3 shaper 33 pulses frequency arrives, is equal to Fj.   FIG.  3 and 4 are diagrams of the variation of the voltage across the outputs 33. 2 and 33. 3 shaper 33 pulses when changing the ratio of the signals from the output of the regulators 20 and 21.  FIG.  4g ampshituda F is larger than amplitude Fj, in FIG.  Зж, з amplitudes are equal, on (би.  4e, w amplitude F,. , and the amplitude Fj is greater than the amplitude of the F ,, ,, Signals from the outputs 33. 2 and 33.3 pulse generator 33 are supplied to the input of control circuit 2, which provides amplification and signal shaping.  The control circuit 2, (FIG.  5) works as follows.  Rectangular pulses from the output of the pulse shaper 33 are fed to the inputs 34. 1 and 34. 2 two-gag lash 34 power fig.  For, b).  At the same time on the primary winding of the pulse transformer 35 (point 35. 1 and 35-2) connected to the outputs 34. 3 and 34. 4, a push-pull power amplifier 34, the signal shown in FIG.  6c On the secondary windings of a pulse transformer 35 (points 35. 3) a signal of exactly the same shape, but with an amplitude in K. . times less. (TO. . -. transformation coefficient of impulse transformer 35).  From each secondary winding of the pulse transformer 35, the signal is fed to the inputs 36.1 and 36. 2 pulse amplifier 36 Consider the operation of a single pulse amplifier 36, since the others work in a similar way.  Signal input 36. 1 and 36. 2 pulse amplifier 36, is fed to the inputs 37.1 and 37. 2, an amplitude detector 37, which emits a positive half wave of the signal, as well as an input 40. 1 and 40. 2 rectifier 40, At the output of the amplitude detector 37 (points 37.3 and 37. 4) a positive polarity signal is generated (FIG.  6d)  Phase. the signal required for proper operation of the output stage transistors is set by phasing the secondary winding of the transformer 35.  From the output of the amplitude detector 37 (point 37. 3 and 37. 4) the signal is fed to the input of the delay delay imager 38, which can be made in the form of a passive EC circuit.  At the exit (38. . 3 and 38. 4) the delay generator 38, the signal shown in FIG.  6e.  The delay time is determined by the state of the RC circuit parameters, the signal from the output of the delaying driver 38, the CI is fed to the input of a pulse amplifier 39 connected to the input of the driver 41, which ensures the formation of a pulse after the delay driver 38.  The shaper 41 can be performed on the logical element I.  At the output of the imaging unit 41, the signal has the form shown in FIG.  6  Here, the delay time Tj is controlled by a potentiometer in the delay driver 38.  Next, the generated signal from the exhaust shaper 41 is fed to the input of the amplifier 42, which amplifies the signal power.  The amplifier 42 can be performed according to the scheme of the unsaturated key.  From the output of amplifier 42 and from the output of pulse amplifier 36 (point 36.3), the signal goes to the base of the corresponding transistor of the output stage (FIG. 1). The output of the corresponding pulse amplifier 36 is connected to the corresponding base of one of the transistors of the output stage.  Rectifier 40 provides the necessary galvanically developed power supply voltage for output stage 39.  This is necessary for normal operation of the output transistors to the scad (FIG.  one).  Thus, the proposed device provides full and independent control of the output pulse width, and therefore, and the voltage amplitude at the outputs of both resonant LC circuits, and this, in turn, provides a change in voltage 5 and current c.  loads.  The use of successive circuits allows the stabilization of current in loads.   In addition, the proposed device provides two independently controlled output voltages with one power output stage, and also stabilizes the output current on both of the two channels.  The device has the linear dependence of the output voltage on the controlled voltage and the possibility of control from the computer through a digital-to-analog converter, which allows the device to be used in automatic process control devices.

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Claims (2)

1. A VOLTAGE CONVERTER containing an output power stage with two groups of transistors, each of which consists of four series-connected transistors, diodes connected in parallel to each of them, two capacitors, the first plates of which are connected to the corresponding input terminals of the output stage, and the second through the recovery diodes connected to the connection points of the transistors of the upper and lower pairs in each group, respectively, and the connection points of each pair of transistors form the output ode power stage, wherein the base of transistors are connected to outputs of the control unit, with the I otlich.ayuschy in that in order to reduce transmitter power by mounting ^one provide two regulated output voltages independent if one power output stage, the integral pulse width administered a modulator, first and second series resonant LC circuits connected in parallel to the output terminals of the power stage, parallel to the capacitors of which are connected output transformers with output frames and filters, while the inputs of the control node are connected to the outputs of the integrated pulse-width modulator. 2. The converter according to π. 1, characterized in that the integrated pulse-width modulator comprises a sinusoidal signal generator assembly, consisting of a rectangular pulse generator connected to the first sinusoidal signal generator, the first output of the node and the input of the frequency divider, the output of which is connected to the second output of the node and the input of the second shaper of a sinusoidal signal, and the outputs of these shapers form the third and fourth outputs of the node, which are connected through two controllers to the inputs of the first comparison node and the first the second two inputs of the control pulse generator, the third and fourth inputs of which are connected respectively to the second and first outputs of the sinusoidal signal generator assembly, the fifth input to the output of the clock generator, the sixth and seventh to the first and third outputs of the first comparison node, the eighth to the output of the second comparison node, the inputs of which are connected to the first and third outputs of the first comparison node, and the outputs of the control pulse shaper are connected to the inputs of the pulse-width modulator, the outputs of which s form the output terminals of the modulator. SU „„ 1121757 1 121757