SU1464274A1 - D.c. to quasisine stepped a.c. voltage converter - Google Patents

Abstract

The invention relates to electrical engineering and can be used in secondary power supply and electric drive systems. The purpose of the invention is to improve the quality of the output, for example, by reducing the content of higher harmonics. The converter contains a main push-pull inverter 19 and additional push-pull inverters 2, 3, 4 with output transformers 11, 12, 13, the secondary windings 14, 15, 16 of which are connected in series and connected to the power supply circuit of the main push pull inverter (between terminals 17 and 18). , - The switching of transistors 5-10 additional push-pull inverters occurs with the help of signals taken from the outputs of the control unit and having a shape corresponding to the Walsh function equal to and a multiple of four. The 19-step pulsating voltage formed at the input of the main push-pull inverter is inverted, and a four-step voltage with the lowest harmonic 15th and harmonic factor of 11.5% is formed at the output of this inverter. 3 il. & SO (: nd 4

Description

The invention relates to electrical engineering and can be used in secondary power supply and electric drive systems.

The purpose of the invention is to improve the quality of the output voltage by reducing the content of higher harmonics.

FIG. 1 is a schematic diagram of the proposed device; in fig. 2 is a circuit diagram of a control unit; in fig. 3 - voltage diagrams.

The device contains a unipolar step voltage driver 1, made in the form of a set of additional push-pull inverters (there are three in the proposed npi-iMepe) 2-4, each of which is performed on transistors 5, 6; 7, 8; 9, 10 and contains the output transformers 11-13, respectively. Secondary windings. These transformers 14-16 are connected in series and connected between the output 17 of the power supply and the same input output 18 of the main push-pull inverter 19.

The main push-pull inverter 19 is made, for example, on a transformer 20 with an average point and on two power transformers 21 and 22.

The control unit 23 consists of serially connected: a generator of 24 clock pulses, a trigger counter 25 with a counting module t, an early 4 (n + 1), where is the number of additional push-pull inverters and a decoder 26 with the number of outputs 2 (n + 1)

FIG. 2, the generator 24 is made according to the scheme of a relaxation generator on a unijunction transistor 27, to the emitter of which a resistor 28 and a capacitor 29 are connected, to the first base a bias resistor 30 is connected, and to the second base there are connected resistors. 31 and 32, which are a voltage divider, the Trigger Point 25 is executed on 1K triggers 33-36 according to the sequential counter of clock pulses fed to the counting trigger 33 from the generator 24 through the inverter 37. From the trigger counter 25 the number of read clock pulses in the binary code (in our example, in four bits) enters decoder 26, which is: a binary code converter of the number 5

50

0

five

0 5 CQ „

clock pulses in the control voltage code of transistor switches 5-10,

21 and 22. In the proposed example, the decoder 26 is made on inverters 38-40, D-flip-flops 41-42 and the EXCLUSIVE OR element 43.

FIG. 3 shows: U is the constant voltage of the stepped form at the output of the driver 1; U ,, is the alternating voltage of a stepped form at the output of the main inverter 19; - control voltages supplied to the bases of the transistors of the additional: 2-4 push pull inverters with the output of the decoder 26; Uj, U control voltages of the power transistors 21 and 22, coming from the outputs of the decoder 26.

The device works as follows.

Additional push-pull cells 2-4 and power transistors 21 and

22 are controlled by the voltages 4l-fg (Fig. 3) coming from the outputs of the decoder 26 in a predetermined sequence: as they count in the trigger counter 25 clock pulses generated by the generator 24. The frequency of the clock pulses of the generator 24 determines the period of the output voltage of the proposed device which is divided into m equal periods of time by a trigger account. 25. 25..

Since the secondary windings of the output transformers of the converter cells are connected in series, the output voltages of the cells are summed, i.e. at the output of the former 1, the unipolar voltage of the step shape U is formed (Fig. 3).

The output voltages of the additional inverters 2–4 are identical in shape to the fourth, eighth, and twelfth Walsh functions, respectively.

The relative transformation ratios of transformers 11–13 (relative to the transformer ratio of transformer 20), i.e.

N ,, N ,, NU N.,.

N; N., / N

one

13

"20

determine the ratios between the amplitudes of the output voltage levels of the converter, t, e. the degree of approximation of the output voltage to the sinu- so: ideal. When choosing these coefficients .v, .equal N, 0.414; , 0.082; N |, 0,2, the harmonic ratio of the output voltage of the converter takes the minimum value equal to 11.5%, and the number of the highest harmonics closest to the first one in the spectrum is equal to 15.

Claims (1)

Invention Formula Constant voltage-to-quasi-sinusoidal voltage step converter containing a main push-pull inverter, a series of additional push-pull inverters with output transformers and a control unit, the input terminals of each additional clock inverter connected to the input terminals, the secondary windings of you 64274 The additional transformers of two-stroke inverters are connected in series and connected between one of the inverter's input terminals: l and the same-polarized input terminal of the main two-stroke inverter, the second input of which is connected directly to 10 by another input output of the converter, which is different in that, in order to improve the quality of the output voltage by reducing the content of higher harmonics, the control circuit for controlling additional push-pull inverters is connected to the corresponding outputs of the control unit that generates signals like number equal to 41, where i 1,2, 20 3, ..., number for the corresponding additional two-phase inverter. f "fc Vff 13ITe Nmnnm P nm p p p p p g-1 p g . GP GPI-I g-1 I /   GP GP G-1 gp m g GP GPI-I g-1 - t tte.5