RU76183U1 - CONSTANT VOLTAGE CONVERTER TO VARIABLE (OPTIONS) - Google Patents

Abstract

The utility model relates to electrical engineering, in particular, to power converting equipment, and can be used in the development of power supplies. Technical essence: DC voltage is converted to high-frequency using a high-frequency controlled inverter 1, the output voltage of which is transformed, and then converted to low-frequency voltage using a demodulator 2. Demodulator 2 is made according to the inverter circuit on fully controlled keys 3-8 with two-side conductivity. According to the first embodiment, a zero pause is introduced between the half-waves of the output voltage of the inverter 1, during which the pro-tactfully working keys of the demodulator are switched. In the second embodiment, the control unit 17 provides the simultaneous conductive state of all counter-working demodulator keys when they are switched, realizing a forced overlap mode, the duration of which is less than the duration of the specified zero pause between the half-waves of the high-frequency voltage of the inverter unit. The technical result for both options is to increase the reliability of the circuit by eliminating the occurrence of overvoltages on the keys of the demodulator with the concomitant effect of eliminating dynamic losses in the demodulator. 2 n.a.s. f-ly, 6 ill.

Description

The utility model relates to electrical engineering, in particular, to power converting equipment, and can be used in the development of power supplies.

Known three-phase voltage inverter, in which to match the levels of input and output voltages, a three-phase transformer is used [1]. A disadvantage of the known device is the low overall dimensions due to the output transformer operating at a relatively low frequency.

The closest to the device according to the first and second variants of the utility model is a three-phase voltage inverter [2], made in the form of series-connected high-frequency controlled inverter, transformer unit and output demodulator, made according to the bridge circuit of the inverter on fully controlled keys.

A disadvantage of the known device [2] is the low reliability due to the possibility of an emergency in the circuit due to high overvoltages on the controlled keys of the AC demodulator that occur when they switch (due to the lack of circuits for the reactive current of the inductive load).

The technical result that can be achieved using the utility model for both of its options is to increase the reliability of the device.

The technical result according to the first embodiment of the utility model is achieved due to the fact that, in a DC-to-AC converter containing a high-frequency controlled inverter unit, the output of which through the transformer unit is connected to the input terminals of a three-phase controlled demodulator made according to an inverter circuit that converts high-frequency voltage to low frequency voltage in accordance with the algorithm specified by the control unit, fully controllable demodulator keys have a two-way nney conductivity, and the control unit ensures the formation of zero pause between half waves of the output voltage of the inverter unit, for which operating keys protivotaktno switched demodulator, wherein the zero pause duration α _Δ is chosen from the condition:

α _Δ = (θ _Δ + α) [electric city],

where: θ _Δ is the fixed minimum zero pause, α is the angle of regulation of the controlled inverter.

The technical result according to the second embodiment of the utility model is achieved due to the fact that in the DC-to-AC converter containing a high-frequency controlled inverter unit, the output of which through a transformer is connected to the input terminals of a three-phase controlled demodulator made according to the inverter circuit that converts high-frequency voltage to low voltage frequencies in accordance with the algorithm specified by the control unit, moreover, fully controlled demodulator keys have two-way conduction, and the control unit is configured to create a zero pause between the half-waves of the output voltage of the inverter unit, during which the counter-working demodulator keys are switched, and at the same time the concurrent state of all counter-working demodulator keys when they are switched, the duration of which is less than the duration of the zero pause poison between the half-waves of the output voltage of the inverter unit, which is selected from the condition:

α _Δ = (θ _Δ + α) [electric city]

where: θ _Δ is the fixed minimum zero pause, α is the angle of regulation of the controlled inverter.

Both variants of the utility model that differ in the functionality of the control unit (in the second embodiment of the utility model, the control unit additionally forms a forced overlap of the conductive state of all the keys of the demodulator when they are switched), are combined by a single technical concept aimed at achieving the same technical result - increasing the reliability of operation devices by eliminating the occurrence of overvoltages on the keys of the demodulator.

Figure 1 presents a diagram of a DC-to-AC converter (for both options).

Figure 2 shows a diagram of a control unit of the Converter for the first embodiment. For the first option, the output signals of the control unit are pulses .

Figure 3 shows a diagram of a control unit of the Converter for the second embodiment. For the second option, the output signals of the control unit are pulses .

Figure 4 and figure 5 shows the timing diagrams explaining the principle of formation of the output voltage and the algorithms of the elements of the control unit.

Figure 6 shows the timing diagrams of the pulse expander.

The device according to both embodiments (Fig. 1) contains two series-connected converting links - a high-frequency controlled inverter 1 with a transformer output and a demodulator 2, made on fully controllable keys 3-8 of alternating current with two-side conductivity. High-frequency inverter 1 consists of two inverter cells, made according to the zero circuit. The first of the cells contains a semiconductor part 9 and a transformer 10 with primary 11 and secondary 12 windings, and the second contains a semiconductor part 13 and transformer 14 with primary 15 and secondary 16 windings. The secondary windings 12 and 16 are connected in series and connected to the power input terminals m, l of the demodulator 2. The connection point of the windings 12, 16 forms the zero output O1 of the circuit. The keys of the high-frequency inverter 1 and demodulator 2 are switched by the signals generated by the control unit 17 (ψ ₁ ... ψ ₄ and ( ) respectively). To improve the quality of the converted electricity, a three-phase L-shaped LC filter 18 can be installed at the output of the demodulator 18. A three-phase load 19 (with zero output О2) is connected either to the three-phase output (A2, B2, C2) of the filter 18 or directly to the three-phase output (A1, B1, C1) demodulator 2.

The control unit according to both variants of execution (Figs. 2, 3) comprises a frequency adjuster 20, the output of which is connected to the input of the frequency divider 21, with paraphase outputs connected to the input of the first pulse distributor 22, which is made according to a ring conversion circuit. The high-frequency unit contains a second pulse distributor 23, connected to the paraphase output terminals of the frequency adjuster 20. The pulse width modulator 24 is made in the form of a sawtooth voltage generator (GPN) 25 and voltage adjuster 26, the outputs of which are connected to the inputs of the first comparator 27. Input of the voltage adjuster 26 is connected to the output of the comparison node 28 of two voltages - the set voltage U ₀ and voltage U _DN from the output voltage sensor (when it is stabilized). For the logical inversion of the signal S (from the output of the first comparator), the logical element "NOT" 29 is used. The logical block of multiplying 30 output pulses of the node 23 and the output pulses of the pulse distributor 22 is made in the form of 6 logical elements "2I" 31 ... 36, three logical “2OR” elements 37, 38, 39 and three “NOT” logical elements 40, 41, 42. The connections between nodes 22, 23, 30 and between logical elements inside block 30 are determined by logical expressions:

The logical node of the distribution of pulses 43, is made in the form of 4 logical elements "2I" 44 ... 47, 2 logical elements "2OR" 48, 49 and two logical elements "NOT" 50, 51. Communication node 43 with nodes 23, 24 and

logical elements inside node 43 are determined by the following logical expressions:

The control unit 3 (according to the second embodiment), completely repeating the circuit of FIG. 2, further comprises a pulse expander 52, which extends the functions of the control unit, providing additional opportunities to increase the reliability of the device by eliminating overvoltages on the demodulator keys.

The pulse expander 52 (Fig. 3) is made in the form of a setter of a minimum fixed pause 53, a second comparator 54 and six logical elements OR 55 ... 60. One input of the comparator 54 is connected to the output of the GPN 25, the second input is connected to the output of the element 53, and the output is connected to one of the inputs of the “2OR” logic elements 55 ... 60, the other inputs of which receive the corresponding signals from the outputs of the logical multiplication unit 30. The output signal ΔS of the comparator 54 has the form of narrow pulses of duration δ (Fig.6). The described logical relationships are determined by the following logical expressions:

Extended pulses are removed from the outputs of the pulse expander key management AC 3 ... 8 demodulator 2. The principle of operation of the expander is illustrated in Fig.6 on the example of pulse expansion and . In the real block diagram of FIG. 2, instead of signals and signals are used .

With strictly synchronous antiphase switching of the keys of each pair in each of the three racks of the bridge of the demodulator 2, a pulse expander 52 is in principle not required. If this condition is not realized, but practically it is not realized, then using the pulse expander 52, a forced overlap mode is introduced, which ensures the simultaneous conductive state of the counter-working demodulator keys when they are switched. The duration of this mode is selected less than the duration of the zero pause α _Δ between the half-waves of the high-frequency voltage of the inverter unit. The introduction of the overlap mode when switching the counter-operating keys of the demodulator 2 eliminates overvoltages caused by the reactive load current with an inductive nature.

Figure 4 presents the timing diagrams of work processes for the case when the multiplicity of the high frequency f of the intermediate conversion

relative to the output frequency F taken small . Equivalent modulating effect (EMW) for each phase

in a compact form, which characterizes the quantization law of the transformed energy flow in it, contains a constant component. This ratio ξ is unacceptable, for example, if in the drivers for the keys of the demodulator 2 galvanic isolation is carried out using transformers. In order to avoid such a regime, the number ξ in this case must satisfy two conditions: it must be, firstly, a multiple of 3, and, secondly, be even. If the drivers are galvanically isolated optically, the number ξ may not be even (but, as before, a multiple of three),

Figure 4 shows:

- two versions of the pulses (6F and 3F) at the input of the frequency divider 21, illustrating two possible options for the construction of the pulse distributor 22;

- - pulses at the output of the pulse distributor 22, (shifted between themselves sequentially at an angle of 2π / 3);

- U _ml - the total voltage of the secondary windings 12, 16 of the transformers 10, 14;

- U _A1О1 , U _B1О1 , U _C1О1 - phase voltages at a three-phase load in the presence of a neutral wire 01-0,

- ψ ₁ ... ψ ₄ - equivalent algorithms for switching counter-working keys 3, 4, 5 and 6, 7, 8 of demodulator 2 (without extension of control pulses);

- U _A2О2 - voltage and i _A2О2 - current at RL load of one phase (A2) in the absence of neutral wire 01-02 and output filter 18.

Figure 5 presents:

- - paraphase pulses at the output of the frequency adjuster 34;

- U _GPN - the output voltage of the sawtooth voltage generator (GPN) 25 and the output voltage U _{a of the} master level 26 output voltage;

- S - pulses at the output of the comparator 27;

- - pulses at the output of the logic element 29;

- - paraphase pulses at the outputs of the pulse distributor 23, (shifted between themselves by an angle π \ 2);

- S · f ¹¹ - pulses at the output of the logic element 45;

- - pulses at the output of the logic element 46;

- - pulses at the output of logic element 47;

- ψ _A , ψ _B and ψ _C - key switching algorithms for high-frequency inverter cells 9, 13, respectively;

- U _ml - voltage at the input of the demodulator.

Figure 6 shows the principle of pulse expansion:

- U _GPN , U _Δ - voltage at the output of the GPN 25 and at the output of the pause master 53;

- ΔS - pulses at the output of the comparator 54 of duration δ;

- - pulses to be expanded;

- - pulses after pulse expansion and .

The logical function of the expansion of the desired pulse, for example is realized by forming (using nodes 25, 53, 54) a pulse train ΔS of duration δ and then feeding them to one of the inputs of a 2 OR logic element, to the second input of which pulses . 2, this expansion function is implemented for six pulses ( ) key management 3 ... 8 demodulator. For this, 6 logical elements 2 OR 55 ... 60 are used.

The device operates as follows.

The high-frequency voltage U _ml at the input terminals m, l of demodulator 2 is in the form of rectangular pulses with a zero pause θ between its half-waves. It is formed by a high-frequency inverter 1, which at a low value of the supply voltage (E _P 12 ... 30V), it is advisable to perform in the form of two inverter cells 9, 13 with a transformer output. Inverter cell keys are controlled by signals which are formed by the nodes 23, 24, 43 of the control unit 17.

Transformers 10, 14 provide voltage increase to the required level. Zero pause α _Δ = (θ _Δ + α) [electric grad.] Is formed due to a symmetric phase shift by an angle (θ _Δ + α) / 2 in opposite directions of the voltage of one inverter cell relative to the other with their subsequent summation in the output circuit of the transformers . With such a change in the angle θ _Δ + α, the phase position of the resulting voltage U _ml does not change, which makes it possible to switch keys 3 ... 8 of the demodulator (at moments corresponding to the middle of zero pauses) for any value of the control angle α. The change in the angle of regulation within α _Δ = θ _Δ ÷ (π / 2-θ _Δ ) provides a change in voltage U _ml from the maximum value to 0.

Minimum pause θ _Δ between half-waves of high-frequency voltage (contributing to the reduction of dynamic losses in the demodulator keys)

corresponds to the maximum voltage U _ml and is determined by the specified signal duration S (Fig.2, 3). In practice, it should be between 2 and 4 microseconds.

When the output voltage is stabilized, its level is set by the signal (setpoint) U ₀ supplied to one input of the comparison unit 28, to the other input of which the signal U _ДН is supplied from the output voltage sensor (it is not shown in the diagrams).

In the presence of a neutral wire 01-02 (Fig. 1), the demodulator 2 operates as follows: within the 1st positive half-wave of the output voltage U _A101 (Fig. 3) of the demodulator, its keys 3, 4 are switched with a frequency f. At the same time, the operation of this pair of keys is similar to the work of a pair of diodes in a conventional rectifier made according to the zero scheme: the positive half-wave of voltage U _{ml is} connected to phase A2 using key 3, and its negative half-wave is using key 4. To change the polarity of the low-frequency voltage U _A101 within its 2nd half-wave, the order of operation of keys 3, 4 is reversed: with the help of key 3, the negative half-wave of the high-frequency voltage U _{ml is} connected to phase A2, and with the help of key 4, its positive half-wave. Essentially, a single-phase demodulator circuit is a single-phase two-half-wave reversible rectifier circuit. The operation of the keys of the other two phases of the demodulator is similar, with the only difference being that the half-wave sign reversal of the low-frequency voltages U _B101 and U _C101 (with frequency F) is carried out with a sequential phase shift by an angle of 2π / 3 (at the output low frequency) relative to voltage U _A101 .

In the absence of a neutral wire 01-02 (Fig. 1), the voltage of phase A2 takes the form U _A101 , shown in Fig. 4.

The algorithm for generating output voltages U _A101 , U _B101 , U _C101 in a formalized form can be described by the following expressions:

where ψ _A , ψ _B , ψ _C are equivalent key switching algorithms 3, 4; 5, 6; 7, 8 (respectively for phases A1, B1, C1, as already mentioned above), which have the form of alternating rectangular pulses with a unit amplitude. The validity of the description (1) can be easily verified by visually multiplying the corresponding signals in Fig. 4.

In addition, we explain the physical essence of the signals and equivalent key switching algorithms. Signals A, B, C in the code "0-1" determine the key switching algorithms 3, 5, 7, and the signals in the same code, demodulator key switching algorithms 4, 6, 8. Since the keys of one rack are switched in counter-tactic (in the absence of overlap in the switchings), the following expressions are valid for the switching algorithms of keys of one phase:

Expressions (2) indicate that the conductivity of the transforming path of the demodulator remains unchanged.

The difference of these signals is an alternating signal:

and is an equivalent key switching algorithm (quantization algorithm or changing the sign of the energy flow) of the corresponding phase. The formalized description is convenient for describing the process of converting one (high) frequency f to another (low) frequency F.

On the 1st interval θ ₀ ÷ θ ₁ (Fig. 3), the voltage U _ml at the input of the demodulator has a negative polarity (with the “-” sign at the top, at point t, the “+” sign at the bottom, at point l in FIG. .one). In accordance with the equivalent algorithms ψ _A , ψ _B , ψ _C , the following demodulator keys are included: in phase A1, key 4, in phase B1, key 5, in phase C1, key 8. At time θ ₁ (in the middle of a zero pause α _Δ ) keys 4, 5, 8 are turned off, and keys 3, 6, 7 are turned on. Keys 3, 6, 7 remain switched on in the interval θ ₁ ÷ θ ₂ that is: during the remaining half pause, during the next voltage pulse U _{ml, it is} already of another, positive polarity (the “+” sign is at the top, the “-” sign is at the bottom ) and during the next half pause. At θ _2, keys 3, 6, 7 are turned off, and keys 4, 5, 8 are turned on again. Thus, the key switching algorithm 3 ... 8 is completely determined by the functions ψ _A , ψ _B , ψ _C , and positive pulses determine the odd key switching algorithms of the corresponding phase racks of the demodulator, and negative pulses determine the even key switching algorithms of the same racks.

Switching of keys occurs at zero values of the switched voltage. As a result of this overvoltage on the keys are absent (which increases the reliability of the circuit), and the dynamic losses in the keys are reduced to zero.

In practice, it is not possible to realize the ideal synchronous antiphase switching of the demodulator keys. As a result, such a situation is not excluded that, in the switching interval, their resulting resistance for the load current may increase. With the inductive nature of the load current, this circumstance can lead to emergency pulse overvoltage on the keys of the demodulator. To eliminate the emergency situation, it is necessary to limit the increase in the resulting key resistance for the load current. For this purpose, the control unit 17 provides the simultaneous conductive state of the counter-working demodulator keys when they are switched, realizing the forced overlap mode described in the second embodiment of the utility model.

The guaranteed overlap mode (the duration of which is shorter than the length of the zero pause α _Δ between the half-waves of the high-frequency voltage of the inverter 1) is carried out due to the fact that the locking switch is supplied with a delay pulse with a delay by an angle δ / 2, and the switching pulse with a delay pulse ahead of the same angle δ / 2. Technology

the formation of such pulses is illustrated in Fig.6, and the implementation is shown in Fig.3 (in the pulse expansion unit 52).

In the middle of zero pauses in the switched voltage U _ml on the interval δ, the simultaneous open state of all six keys of the demodulator is realized, which provides a path for the free flow of the load for the reactive current, as a result of which overvoltages do not occur on the keys.

Thus, (in the scheme of the utility model according to the first embodiment), by introducing a zero pause between the half-waves of the output voltage of the high-frequency inverter, it became possible to switch the demodulator keys at zero voltage values U _ml , which eliminates the occurrence of overvoltages on their power electrodes, and, therefore, increases reliability of the device.

The introduction of a forced overlap mode δ (according to the second embodiment) in the middle of a zero pause organizes the inductive load reactive current circuit, which also eliminates the occurrence of overvoltage on the keys and further increases the reliability of the device.

The high reliability of the circuit elements allows it to be most preferable when developing schemes of power supplies for a wide range of purposes.

Sources of information taken into account when compiling the description:

1. B.C. Moin “Stabilized Transistor Converters” M., ENERGOATOMIZDAT, 1986

2. Ibid., P. 344.

Claims (2)

1. A DC-to-AC converter containing a high-frequency controlled inverter unit, the output of which through a transformer unit is connected to the input terminals of a three-phase controlled demodulator made according to an inverter circuit that converts high-frequency voltage to low-frequency voltage in accordance with the algorithm specified by the control unit, when This fully controlled demodulator keys have two-sided conductivity, and the control unit is designed to generate zero the pause between half-waves of the output voltage of the inverter unit, during which the counter-working demodulator keys are switched, and the duration of the zero pause α _{Δ is} selected from the condition α _Δ = (θ _Δ + α) [email. hail], where θ _Δ , is the fixed minimum zero pause, α is the angle of regulation of the controlled inverter. 2. A DC-to-AC converter containing a high-frequency controlled inverter unit, the output of which through a transformer is connected to the input terminals of a three-phase controlled demodulator made in accordance with an inverter circuit that converts high-frequency voltage to low-frequency voltage in accordance with an algorithm specified by the control unit, the controlled keys of the demodulator have two-sided conductivity, and the control unit is designed to generate zero pau s between the half-waves of the output voltage of the inverter assembly, during which the switch protivotaktno keyed demodulator and therewith simultaneously conducting state all protivotaktno working demodulator key when shifting, whose duration is shorter than the zero pause α _Δ between the half-waves of the output voltage of the inverter unit, which is selected from the condition α _Δ = (θ _Δ + α) [email. hail], where θ _Δ is a fixed minimum zero pause, α is the angle of regulation of the controlled inverter.