RU2366068C1 - Method of converting direct voltage to alternating voltage - Google Patents

Abstract

FIELD: electrical engineering.

SUBSTANCE: invention relates to electronics, particularly to power transformation technology, and can be used in designing electrical power supplies. Direct voltage is converted to high-frequency voltage using a high-frequency controlled inverter (1), output voltage of which is transformed and then converted to low-frequency voltage using a demodulator (2). The demodulator (2) is made from an inverter circuit on fully controlled switches (3-8) with two-way conductivity. Between half-waves of output voltage of the inverter (1) a zero pause is created using a control unit (17), during which anti-stroke operating switches of the demodulator are switched. Duration of the zero pause includes a fixed minimum component and a varying component, which depends on the regulation angle of the high-frequency inverter. The control unit (17) also provides for simultaneous conducting state for all anti-stroke operating switches of the demodulator during their switching, duration of which is less than duration of the zero pause.

EFFECT: increased reliability of operation by prevention of excess voltage across demodulator switches during their switching with by-effect of reducing dynamic loss in the demodulator.

2 cl, 5 dwg

Description

The invention relates to electrical engineering, in particular to power converting equipment, and can be used in the development of power supplies with improved quality indicators.

A known method of converting DC voltage to AC, which consists in the fact that using an inverter form a three-phase AC voltage of a rectangular shape, which is transformed and transferred to the load [1]. Coordination of input and output voltage levels is carried out using a three-phase transformer operating at an output low frequency (50 Hz, 400 Hz), which leads to a deterioration in the overall dimensions of the device.

Closest to the invention, the technical solution is a method for converting direct voltage to alternating voltage, which means that the direct voltage is converted to high-frequency using a controlled inverter, the output voltage of which is transformed and then again converted to low-frequency voltage in accordance with the algorithm specified by the control unit. The conversion of high-frequency voltage to low-frequency is carried out using a demodulator made according to the inverter circuit on fully controllable keys of alternating current with two-sided conductivity [2].

The disadvantage of this method of conversion [2] is the low reliability due to the possibility of an emergency in the circuit due to high overvoltages on the controlled keys of the AC demodulator that occur when they are switched (due to the absence of reactive current circuits of the inductive load) .

The technical result that can be achieved by using the invention is to increase the reliability of the device.

The technical result is achieved due to the fact that in the method of converting dc voltage to ac, which consists in converting dc voltage to high frequency using a high-frequency controlled inverter, the output voltage of which is transformed, and then converted to low frequency voltage, changing in accordance with a given the algorithm control unit using a demodulator made according to an inverter circuit on fully controlled keys with two-sided conductivity (2), between the floor by the output voltage waves of the high-frequency inverter, a zero pause is entered using the control unit, during which the counter-working demodulator keys are switched, and the duration of the zero pause α _{Δ is} selected from the condition:

α _Δ = θ _Δ + α [el. hail],

where α is the angle of regulation of the output voltage of the controlled inverter,

θ _Δ is a fixed minimum zero pause.

Moreover, the control unit can additionally provide a simultaneous conductive state of all counter-working demodulator keys when they are switched, the duration of which is less than the duration of the zero pause between the half-waves of the high-frequency voltage of the inverter unit.

From sources of information, there is a known way to increase the reliability of operation of counter-working inverter keys by introducing a zero pause between the commands to switch them (see. BC BC Moin and NN Laptev “Stabilized Transistor Converters” M .: Energy, 1972) However This method is aimed at solving the problem of eliminating the through currents that occur when switching counter-working keys. It cannot be used in this demodulator circuit, because the introduction of pauses between control signals inevitably leads to the appearance of overvoltages on the keys, leading to an emergency state of the circuit elements (due to the inductive nature of the load). On the keys of this modulator, the appearance of overvoltages is fundamentally impossible, because they switch when the voltage on them is zero. Thus, from the known sources of information does not follow the obviousness of using the well-known technical methods in this invention, which allows us to conclude that this method meets the criterion of "inventive step".

Figure 1 presents a diagram of a three-phase DC-AC to AC converter that implements this conversion method.

Figure 2 shows the functional diagram of the control unit of the Converter.

Figure 3 and figure 4 shows the timing diagrams explaining the principle of formation of the output voltage and the algorithms of the elements of the control unit.

Figure 5 shows the timing diagrams of the operation of the pulse expander.

, B,

, C,

соответственно). Для улучшения качества преобразованной электроэнергии на выходе демодулятора может устанавливаться трехфазный Г-образный LC фильтр 18. Трехфазную нагрузку 19 (с нулевым выводом O2) подключают или к трехфазному выходу (A2, B2, C2) фильтра 18, или непосредственно к трехфазному выходу (A1, B1, C1) демодулятора 2.The device (Fig. 1) contains two series-connected converting links - a high-frequency controlled inverter 1 with a transformer output and a demodulator 2, made on fully controllable switches 3 ÷ 8 of alternating current with two-side conductivity. High-frequency inverter 1 consists of two inverter cells, made according to the zero circuit. The first of the cells contains a semiconductor part 9 and a transformer 10 with primary 11 and secondary 12 windings, and the second contains a semiconductor part 13 and transformer 14 with primary 15 and secondary 16 windings. The secondary windings 12 and 16 are connected in series and connected to the power input terminals m, l of the demodulator 2. The connection point of the windings 12, 16 forms the zero output O1 of the circuit. The keys of the high-frequency inverter 1 and demodulator 2 are switched by the signals generated by the control unit 17 (ψ ₁ ... ψ ₄ and A,

, B,

, C,

respectively). To improve the quality of the converted electricity, a three-phase L-shaped LC filter 18 can be installed at the output of the demodulator 18. The three-phase load 19 (with zero output O2) is connected either to the three-phase output (A2, B2, C2) of the filter 18, or directly to the three-phase output (A1, B1, C1) demodulator 2.

The control unit (figure 2) contains a frequency adjuster 20, the output of which is connected to the input of the frequency divider 21, by the paraphase outputs connected to the input of the first pulse distributor 22, which is made according to a ring conversion circuit. The high-frequency unit contains a second pulse distributor 23, connected to the paraphase output terminals of the frequency adjuster 20. The pulse width modulator 24 is made in the form of a sawtooth voltage generator (GPN) 25 and voltage regulator 26, the outputs of which are connected to the inputs of the first comparator 27. Input of voltage regulator 26 connected to the output of the comparison node 28 of two voltages - the set voltage U ₀ and voltage U _DN from the output voltage sensor (when it is stabilized). For the logical inversion of the signal S (from the output of the first comparator), the logical element "NOT" 29 is used. The logical unit of multiplying 30 output pulses of the node 23 and the output pulses of the pulse distributor 22 is made in the form of 6 logical elements "2I" 31 ... 36, three logical elements " 2OR ”37, 38, 39 and three logical elements“ NOT ”40, 41, 42. The connections between nodes 22, 23, 30 and between logical elements inside block 30 are determined by logical expressions:

,

,

,

,

The logical node of the distribution of pulses 43 is made in the form of 4 logical elements "2I" 44 ... 47, 2 logical elements "2OR" 48, 49 and two logical elements "NOT" 50, 51. Communication node 43 with nodes 23, 24 and logical elements inside node 43 are defined by the following logical expressions:

,

,

,

,

,

,

The pulse expander 52 is made in the form of a setter minimum fixed pause 53, the second comparator 54 and six logical elements OR 55 ... 60. One input of the comparator 54 is connected to the output of the GPN 25, the second input to the output of the element 53, and the output to one of the inputs of the logic elements “2OR” 55 ... 60, the other inputs of which receive the corresponding signals from the outputs of the logical multiplication unit 30. The output signal ΔS of the comparator 54 has the form of narrow pulses of duration θ _Δ (Fig. 5). The described logical relationships are determined by the following logical expressions:

, В¹,

, С,

для управления ключами переменного тока 3…8 демодулятора 2. Принцип работы расширителя поясняется на фиг.6 на примере расширения импульсов f¹ и

. В реальной блок-схеме на фиг.2 вместо сигналов f¹ и

используются сигналы А,

, В,

, С,

.From the outputs of the pulse expander 52 remove the extended pulses And ¹ ,

, In ¹ ,

, FROM,

to control the AC keys 3 ... 8 demodulator 2. The principle of operation of the expander is illustrated in Fig.6 on the example of the expansion of pulses f ¹ and

. In the real block diagram of FIG. 2, instead of signals f ¹ and

signals A are used,

, AT,

, FROM,

.

With perfect synchronous antiphase switching of the keys of each pair in each of the three pillars of the bridge of the demodulator 2, a pulse expander 52 is in principle not required. If this condition is not realized, which is the case in practice, then with the help of the pulse expander 52, a forced overlap mode is introduced, which ensures the simultaneous conductive state of the counter-working demodulator keys when they are switched. The duration of this mode δ is chosen less than the duration of the minimum zero pause θ _Δ between the half-waves of the high-frequency voltage of the inverter unit. The introduction of the overlap mode when switching the counter-operating keys of the demodulator 2 eliminates overvoltages caused by the reactive load current with an inductive nature.

. Эквивалентное модулирующее воздействие (ЭМВ) для каждой фазыFigure 3 presents the timing diagrams of work processes for the case when the multiplicity of the high frequency f of the intermediate conversion relative to the output frequency F is taken small -

. Equivalent modulating effect (EMW) for each phase

,

,

,

,

in a compact form, which characterizes the quantization law of the transformed energy flow in it, contains a constant component. This ratio ξ is unacceptable, for example, if in the drivers for the keys of the demodulator 2 galvanic isolation is carried out using transformers. In order to avoid such a regime, the number ξ in this case must satisfy two conditions: it must be, firstly, a multiple of 3, and, secondly, be even. If the drivers are galvanically isolated optically, the number ξ may not be even (but, as before, a multiple of three).

Figure 3 shows:

- two variants of pulses (6F and 3F) at the input of the frequency divider 21, which reflect two possible options for the construction of the pulse distributor 22;

, p₂,

, p₃,

- импульсы на выходе распределителя импульсов 22, (сдвинутые между собой последовательно на угол 2π/3);- p ₁ ,

, p ₂ ,

, p ₃ ,

- pulses at the output of the pulse distributor 22, (shifted between themselves sequentially at an angle of 2π / 3);

- U _ml - the total voltage of the secondary windings 12, 16 of the transformers 10, 14;

- U _A1O1 , U _B1O1 , U _C1O1 - phase voltages at a three-phase load in the presence of a neutral wire 01-0;

- ψ _A , ψ _B , ψ _C - equivalent switching algorithms of counter-working keys 3 and 4; 5 and 6; 7 and 8 of demodulator 2 (without expansion of control pulses);

- U _A2O2 - voltage and i _A2O2 - current at RL load of one phase (A2) in the absence of neutral wire 01-02 and output filter 18.

Figure 4 presents:

- парафазные импульсы на выходе задатчика частоты 34;- 2f ¹ and

- paraphase pulses at the output of the frequency adjuster 34;

- U _GPN - the output voltage of the sawtooth voltage generator (GPN) 25 and the output voltage U _{α of the} master level 26 output voltage;

- S - pulses at the output of the comparator 27;

- импульсы на выходе логического элемента 29;-

- pulses at the output of the logic element 29;

и f¹¹,

- парафазные импульсы на выходах распределителя импульсов 23, (сдвинутые между собой на угол π\2);- f ¹

and f ¹¹ ,

- paraphase pulses at the outputs of the pulse distributor 23, (shifted between themselves by an angle π \ 2);

- S · f ¹¹ - pulses at the output of the logic element 45;

- импульсы на выходе логического элемента 46;-

- pulses at the output of the logic element 46;

- импульсы на выходе логического элемента 47;-

- pulses at the output of logic element 47;

- ψ ₁ , ψ ₂ and ψ ₃ , ψ ₄ - key switching algorithms for high-frequency inverter cells 9, 13, respectively;

- U _ml - voltage at the input of the demodulator.

Figure 5 shows the principle of pulse expansion

- U _GPN , U _Δ - voltage at the output of the GPN 25 and at the output of the pause master 53;

- ΔS - pulses at the output of the comparator 54 of duration δ;

- импульсы, подлежащие расширению;- f ¹ and

- pulses to be expanded;

) - импульсы после расширения импульсов f¹ и

.- (f ¹ + ΔS), (

) - pulses after the expansion of pulses f ¹ and

.

, В,

, С,

) управления ключами 3…8 демодулятора. Для этого используются 6 логических элементов 2ИЛИ 55…60.The logical function of expanding the required pulse, for example, f ¹ , is realized by forming (using nodes 25, 53, 54) a pulse train ΔS of duration δ (Fig. 5) and then feeding them to one of the inputs of the 2 OR gate, to the second input of which pulses f ¹ . In figure 2, this expansion function is implemented for six pulses (A,

, AT,

, FROM,

) key management 3 ... 8 demodulator. For this, 6 logical elements 2 OR 55 ... 60 are used.

The device operates as follows.

The high-frequency voltage U _ml at the input terminals m, l of demodulator 2 is in the form of rectangular pulses with a zero pause α _Δ ≥θ _Δ between its half-waves. It is formed by a high-frequency inverter 1, which at a low value of the supply voltage (E _P = 12 ... 30 V), it is advisable to perform in the form of two inverter cells 9, 13 with a transformer output. The keys of the inverter cells are controlled by the signals ψ ₁ , ψ ₂ , ψ ₃ , ψ ₄ , which are formed by the nodes 23, 24, 43 of the control unit 17.

Transformers 10, 14 provide voltage increase to the required level. Zero pause α _Δ = (θ _Δ + α) [email. deg] is formed due to a symmetric phase shift by an angle α _Δ / 2 in opposite directions of the voltage of one inverter cell relative to another, followed by their summation in the output circuit of the transformers. With such a change in the angle α _{Δ, the} phase position of the resulting voltage U _ml does not change, which makes it possible to switch 3 ... 8 keys of the demodulator (at the moments corresponding to the middle of zero pauses) at any value of the control angle α _Δ . Changing it within α = θ _Δ ÷ (π / 2-θ _Δ ) provides a change in voltage U _ml from the maximum value to 0.

The minimum pause θ _Δ between the half-waves of the high-frequency voltage (also contributing to the reduction of dynamic losses in the keys of the demodulator) corresponds to the maximum voltage U _ml and is determined by the set signal duration S (Fig. 2). In practice, it should be from 2 to 4 microseconds (depending on the frequency properties of the transistors).

When the output voltage is stabilized, its level is set by the signal (setpoint) U ₀ supplied to one input of the comparison unit 28, to the other input of which the signal U _ДН is supplied from the output voltage sensor (it is not shown in the diagrams).

In the presence of a neutral wire 01-02 (Fig. 1), the demodulator 2 operates as follows: within the 1st positive half-wave of the output voltage U _A101 (Fig. 3) of the demodulator, its keys 3, 4 are switched with a frequency f. In this case, the operation of this pair of keys is similar to the operation of a pair of diodes in a conventional rectifier made according to the zero scheme: a positive half-wave of voltage U _{ml is} connected to phase A1 using a key 3, and a negative half-wave of it is using a key 4. To change the polarity of the low-frequency voltage U _A101 within its 2nd half-wave, the order of operation of keys 3, 4 is reversed: with the help of key 3, the negative half-wave of the high-frequency voltage U _{ml is} connected to phase A1, and with the help of key 4, its positive half-wave. Essentially, a single-phase demodulator circuit is a single-phase two-half-wave reversible rectifier circuit. The operation of the keys of the other two phases of the demodulator is similar, with the only difference being that the half-wave sign reversal of the low-frequency voltages U _B101 and U _C101 (with frequency F) is carried out with a sequential phase shift by an angle of 2π / 3 (at the output low frequency) relative to voltage U _A101 .

In the absence of a neutral wire 01-02 (Fig. 1), the voltage of phase A2 takes the form U _A202 , shown in Fig. 3.

The algorithm for generating output voltages U _A101 , U _B101 , U _C101 in a formalized form can be described by the following expressions:

,

,

,

,

where ψ _A , ψ _B , ψ _C are equivalent key switching algorithms 3, 4; 5, 6 and 7, 8 (respectively, for phases A1, B1, C1, as was mentioned above), which have the form of alternating rectangular pulses with a unit amplitude. The validity of the description (5) can be easily verified by visually multiplying the corresponding signals in Fig. 3.

, B,

, C,

и эквивалентных алгоритмов переключения ключей. Сигналы A, B, C в коде «0-1» определяют алгоритмы переключения ключей 3, 5, 7, а сигналы

,

,

в том же коде - алгоритмы переключения ключей 4, 6, 8 демодулятора. Поскольку ключи одной стойки переключают в противотакте (в случае отсутствия перекрытий δ в переключениях), то для алгоритмов переключения ключей одной фазы справедливы следующие выражения:In addition, we explain the physical essence of the signals A,

, B,

, C,

and equivalent key switching algorithms. Signals A, B, C in the code "0-1" determine the key switching algorithms 3, 5, 7, and the signals

,

,

in the same code, demodulator key switching algorithms 4, 6, 8. Since the keys of one rack are switched in counter-tact (in the absence of overlap δ in the switchings), the following expressions are valid for the algorithms for switching keys of one phase:

,

,

,

,

Expressions (6) indicate that the conductivity of the transforming path of the demodulator remains unchanged.

The differences of these signals are alternating signals:

;

;

;

;

and represent an equivalent key switching algorithm (a quantization algorithm or a change in the sign of the energy flux) of the corresponding phase. The formalized description is convenient for describing the process of converting one (high) frequency f to another (low) frequency F.

In the 1st interval θ ₀ ÷ θ _{1, the} voltage U _ml at the input of the demodulator according to Fig. 3 has a negative polarity (the polarity in the circuit in Fig. 1 is as follows: the “+” sign is at point l, the “-” sign is at point m). In accordance with the equivalent algorithms ψ _A , ψ _B , ψ _C , the following demodulator keys are included: in phase A1, key 4, in phase B1, key 5, in phase C1, key 8. At time θ ₁ (in the middle of the zero pause α _Δ ) keys 4, 5, 8 are turned off, and keys 3, 6, 7 are turned on. Keys 3, 6, 7 remain on in the interval θ ₁ ÷ θ ₂ , that is, during the remaining half pause (α _Δ / 2), during the next voltage pulse U _{ml is} already a different, positive polarity (the “+” sign at the point m, the sign “-” - at point l) and during the next half pause. At θ _2, keys 3, 6, 7 are turned off, and keys 4, 5, 8 are turned on again. Thus, the key switching algorithm 3 ... 8 is completely determined by the functions ψ _A , ψ _B , ψ _C , and positive pulses determine the odd key switching algorithms of the corresponding phase racks of the demodulator, and negative pulses determine the even key switching algorithms of the same racks. Switching of keys occurs at zero values of the switched voltage. As a result of this overvoltage on the keys are absent (which dramatically increases the reliability of the circuit), and the dynamic losses in the keys are reduced to zero.

In practice, it is not possible to realize the ideal synchronous antiphase switching of the demodulator keys. As a result, such a situation is not excluded that, in the switching interval, their resulting resistance for the load current may increase. With the inductive nature of the load current, this circumstance can lead to emergency pulse overvoltage on the keys of the demodulator. To eliminate the emergency situation, it is necessary to limit (or exclude) the increase in the resulting key resistance for the load current. For this purpose, the control unit 17 provides a simultaneous conductive state of the counter-operating demodulator keys when they are switched, realizing a forced overlap mode. The guaranteed overlap mode (whose duration δ is less than the duration of the zero pause between the half-waves of the high-frequency voltage of the inverter 1) is carried out due to the fact that the locking switch is supplied with a delay pulse with a delay of δ / 2, and the switching pulse with a delay pulse with an advance of the same angle δ / 2. The technology for generating such pulses is illustrated in FIG. 5, and the implementation in FIG. 3 (in a pulse expansion unit 52).

In the middle of zero pauses in the switched voltage U _ml in the interval δ, the simultaneous open state of all six keys of the demodulator is realized, which provides a path for the load to flow freely and there is no overvoltage on the keys.

Thus, by introducing a zero pause between the half-waves of the output voltage of the high-frequency inverter, it became possible to switch the keys of the demodulator without causing overvoltages (the keys switch at zero supply voltage). The elimination of overvoltage on the demodulator keys during their switching increases the reliability of the device and reduces to zero the dynamic loss in its keys.

The introduction of a forced mode of overlapping the conductive state of counter-operating demodulator keys during a zero pause can further improve operational reliability by eliminating overvoltage on the keys caused by the absence of circuits for closing the reactive current of the inductive load. In addition, the invention eliminates dynamic losses in the demodulator.

High reliability of the elements of the device allows it to be most preferable when developing power supplies for a wide range of purposes.

Information sources

1. Moin B.C. Stabilized transistor converters. M .: ENERGOATOMIZDAT, 1986, p. 379.

2. Ibid., P. 344.

Claims (2)

1. A method of converting direct voltage to alternating voltage, which means that the direct voltage is converted to high-frequency using a high-frequency controlled inverter, the output voltage of which is transformed, and then converted to low-frequency voltage, which is changed in accordance with a given algorithm control unit using a demodulator, made according to the inverter circuit on fully controlled keys with two-sided conductivity, characterized in that between the half-waves of the output voltage you okochastotnogo inverter by the control unit is administered zero pause, during which the switch protivotaktno demodulator operating keys, and a pause duration zero sous conditions selected from:
α _Δ = θ _Δ + α [el. hail.],
where α is the angle of regulation of the output voltage of the controlled inverter;
θ _Δ is a fixed minimum zero pause. 2. The method of converting direct voltage to AC according to claim 1, characterized in that the control unit provides a simultaneous conductive state of all counter-working demodulator keys when they are switched, the duration of which is less than the duration of the zero pause between half-waves of the high-frequency voltage of the inverter unit.

Images