CN1093995C - A fast sigma-delta modulator having controlled clock generator - Google Patents
A fast sigma-delta modulator having controlled clock generator Download PDFInfo
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- CN1093995C CN1093995C CN96193112A CN96193112A CN1093995C CN 1093995 C CN1093995 C CN 1093995C CN 96193112 A CN96193112 A CN 96193112A CN 96193112 A CN96193112 A CN 96193112A CN 1093995 C CN1093995 C CN 1093995C
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
- H03K5/1504—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of active delay devices
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
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Abstract
An apparatus receives a reference clock signal that is then applied to a first one of a number of series-connected controllable delay stages. The output of each delay stage is a further delayed version of its input, the amount of delay being controlled by a control signal. A phase relation between a first preselected one of the plurality of delayed reference clock signals and a second preselected one of the plurality of delayed reference clock signals is measured. Alternatively, it may be a phase relation between the reference clock signal and a preselected one of the plurality of delayed reference clock signals that is measured. The measured phase relation is compared with a desired phase relation, and the difference is an error signal that is fed back to the delay stages for use as the delay control signal. In this manner, the delayed reference clock outputs from the delay stages lock in to a very stable desired phase relation with respect to one another. The delayed reference clocks are then transformed by logic circuitry into nonoverlapping phase clocks for use by a switched capacitor sigma-delta modulator. By using the clocks generated in this manner, the switched-capacitor sigma-delta modulator may be operated at rates of 13 MHz or higher.
Description
Technical field
The present invention relates to controlled clock generator, relate in particular to and be used for the not controlled clock generator of the sigma-delta modulator of overlapping clock.
Background technology
It is known that mould-number (A/D) converter is widely used.Many these application requirements A/D converters have high-resolution and energy high speed operation.In the existing various technology that analog signal are for conversion into digital form, a kind of technology that is called ∑-Δ conversion combined sampling and noise shaping, and it has become a kind of technology that the most often is used.This is to have eliminated needs to accurate and expensive antialiasing filter because cross sampling, if adopt other converter technique, and just need this filter.The structure that the A/D converter 103 that Fig. 1 is illustrated in non-∑-Δ type in the prior art is connected with multiple antialiasing filter 101.
In contrast, Fig. 2 represents the structure of the A/D converter of the ∑-Δ type in the prior art.Multiple antialiasing filter 101 is by much simple that prefilter 201 replaces.After sigma-delta modulator is decimation filter of digital 205.The requirement of prefilter 201 and 203 pairs of tolerance limits of sigma-delta modulator all than multiple 101 pairs of tolerance limits of antialiasing filter require much loose.In addition, the decimation filter of digital 205 after sigma-delta modulator 203 is accurate, is not subjected to the influence of manufacturing process variations.
Sigma-delta modulator also can be integrated in the VLSI integrated circuit of mixed signal.In sort circuit, the noise reshaper in the sigma-delta modulator often utilizes switched capacitor techniques to realize.The United States Patent (USP) that licenses to little Cathy Ferguson people such as (Ferguson) has been described the theoretical and application of the high resolution A/D converter of employing switched capacitor sigma-Delta modulator for the 5 311 No. 181, and this full patent texts is awarded and drawn in this document for referencial use.
Switched capacitor sigma-Delta modulator needs two phase clock for operate as normal.The clock demand of regular tap capacitor sigma-delta modulator as shown in Figure 3.As illustrated, two phase place P1, P2 must be not overlapping.In other words, asserted by separating and the second phase place P2 must have the interval T 1 of non-zero duration after being asserted at the first phase place P1.Similarly, asserted by separating and the first phase place P1 also must have the interval T 2 of non-zero duration after being asserted at the second phase place P2.
A kind of known method that improves the noiseproof feature of switched capacitor filters is that the error voltage that adopts such design will the switch on switched capacitor to introduce reduces to minimum, this design as shown in Figure 4, except that the standard first and second phase clock P1, P2, also need two leading phase clock P1e, P2e.(in the description of some prior art, datum mark is opposite with datum mark described here, so these four phase clocks are believed to comprise first and second phase clock of standard and first and second lagging phase clock.But no matter title how, operating principle is the same.) must settle out in the required time switch in closed this filter at the operational amplifier of switched capacitor filters, electric charge that also must be in change is stored in capacitor is the switch in closed this filter in required time.In Fig. 4, these times are determined by the asserted of each signal.Can find in " the actual consideration that switched-capacitor circuit designs " on " simulation and hybrid integrated circuit actual aspect " 37-61 page or leaf that M.Rebeschini showed that Switzerland Lausanne publishing house publishes 4-8 day in July, 1994 the more detailed discussion of the use of leading phase clock signal in switched capacitor filters, this content is incorporated herein for referencial use.
Though require sigma-delta modulator with very high speed operation in many application, limiting factor is the precision of two phase clock.For example, the time width Tsettle that asserts of each phase clock P1, P1e, P2, P2e was 15 nanoseconds usually at least.The hysteresis T1 of the first phase clock P1 hysteresis leading phase clock P1e was 3 nanoseconds at least.Similarly, the hysteresis T3 of the second phase clock P2 hysteresis leading phase clock P2e also was 3 nanoseconds at least.In addition, during this period neither one phase clock P1, P1e, P2, P2e be asserted not overlapping time T2 and T5 all should to be at least for 3 nanoseconds long.
Therefore, shortest time of needing of a complete cycle Tcycle of four clocks (for example assert the first time of the first leading phase clock P1e 401 and next time the asserting time interval between 403 of this first leading phase clock P1e) is:
Tcycle=2*Tsettle+T1+T2+T3+T5=2 * 15 nanosecond+4 * 3 nanosecond=42 nanoseconds
Can find out that by above formula the theoretical upper limit of the execution speed of switched capacitor sigma-Delta modulator is 1/42 nanosecond=23.8MHz.But any actual design of this modulator all must be considered this fact: the circuit common that promptly produces each phase clock P1, P1e, P2, P2e all has the tolerance limit that allows arbitrary time T 1, T2, T3, T4, T5 and T6 to depart from Len req.This is because each phase clock P1, P1e, P2, P2e are the reference clock of taking from as illustrated in fig. 5 through a series of delay stages 503 501 usually.Fig. 6 represents the signal by this circuit structure generation.The output that each delay stages 503 produces is the reproduction of the input of its quantity Δ of having been delayed time.Reference clock 501 and 7 time delayed signal D1out ... D7out offers the logical circuit that they is become 4 phase clock P1, P1e, P2, P2e.
Common delay stages 503 is illustrated in greater detail in Fig. 7.Input signal 701 offers first inverter apparatus that produces inversion signal 703.Amount of delay depends on how long inversion signal 703 needs are charged to the value that makes second inverter change its output to capacitor 705.Regrettably amount of delay is not constant, but changes with temperature, technique change, power supply and input signal.When needs produced the short time delay of 3 nanoseconds, common time-delay diffusion was the time-delay that can change between 3 nanoseconds and 6 nanoseconds.
Get back to the problem of design speed-sensitive switch capacitor sigma-delta modulator now, the common time-delay diffusion of clock generator is+/-40%.Because above to have obtained admissible short period time Tcycle be 42 nanoseconds, so can expect can produce the formation clock of following long period time to this cycle time as the clock generator of short period time:
Therefore, can not look to adopting the switching capacity sigma-delta modulator of ordinary clock generator to carry out work with the speed faster than 1/98 nanosecond=10.2MHz.
If wish to make switched capacitor sigma-Delta modulator with higher speed work, for example with 13MHz, then admissible long period time T cycle is exactly 1/ (13 * 10
6)=77 nanosecond.This means that the time-delay diffusion that must make clock generator is not inferior to:
Time-delay diffusion=29%
Rather than common 40% time-delay diffusion.But, can not design delay stages 503 at present with this levels of precision.Therefore, ordinary skill has hindered switched capacitor sigma-Delta modulator to carry out work with the clock rate that is much higher than about 10MHz.
Prior art, the United States Patent (USP) that for example licenses to Saleh have been discussed for No. 5349352 to ∑-Δ A/D converter the problem of the reference clock 501 of less noise are provided.In order to eliminate the variable cycle noise, for example from the noise that concentrates on 60Hz of power line, this prior art has been described device shown in Figure 8, in this device, phase-locked loop 803 receives noisy clock signal 801, and produces the less reference clock 805 of noise that offers A/D converter 807.This A/D converter 807 can utilize this reference clock 805 to produce each phase clock P1, P1e, P2, P2e according to the above mode of describing with respect to Fig. 5-7 then.Obviously, because this technology does not have to solve the problem that the delay stages 503 in A/D converter 807 inside produces, so it can not make this A/D converter with very high speed work.In other words, even reference clock 805 can have preferable quality, but still can not look to delay stages 503 accurately to produce very time-delay near desired 3 nanoseconds of short time delay.
Summary of the invention
Therefore, the purpose of this invention is to provide the method and apparatus that produces nonoverlapping clock signal, the quality of these nonoverlapping clock signals is enough to make sigma-delta modulator to utilize the speed of the speed that ordinary skill can realize to carry out work to be higher than widely.According to an aspect of the present invention, above-mentioned and other purpose realizes in such equipment, and this equipment comprises the input unit that receives reference clock signal and the controlled time-delay mechanism that is connected with this input unit, produce a plurality of time-delay reference clock signals according to the reference clock signal that is received.For each of a plurality of time-delay reference clocks, corresponding amount of delay can be controlled by control signal.This equipment also comprises and this input unit and the phase comparator device that is connected with this time-delay mechanism, produce error signal, the size of this error signal be proportional to tested phase relation between one of this reference clock signal that receives and previously selected maximum delay reference clock signal and the bias of predetermined phase relation.In an alternate embodiment, this phase comparator device only is connected with this controlled time-delay mechanism, produces second chosen in advance that its size is proportional to first chosen in advance time-delay reference clock signal of a plurality of time-delay reference clock signals and a plurality of time-delay reference clock signals delay time the tested phase relation between the reference signal and the bias of predetermined phase relation.
In these two embodiment, error signal offers each the control signal of amount of delay of controlled time-delay mechanism as a plurality of time-delay reference clock signals of control.Feed back this error signal in this way, the amount of delay that controlled time-delay mechanism produces just locking becomes a stable quantity.
This equipment also comprises the logic device that produces nonoverlapping first and second phase clock signals according to a plurality of time-delay reference clock signals.In one embodiment of the invention, first phase clock signal comprises the first leading phase clock signal and the first standard phase clock signal, and second phase clock signal comprises the second leading phase clock signal and the second standard phase clock signal.At last, this equipment comprises switched capacitor sigma-Delta modulator device.This switched capacitor sigma-Delta modulator device comprises: the clock input unit that receives nonoverlapping first and second phase clock signals; The signal input apparatus of modulation signal is treated in reception; And comprise switched-capacitor circuit, this treats the device of modulation signal in the control modulated of these nonoverlapping first and second phase clock signals.
By using the not overlapping clock that produces by this way, switched capacitor sigma-Delta modulator can be according to the speed work that is higher than 10MHz (for example 13MHz or higher) widely.
According to another aspect of the present invention, controlled time-delay mechanism comprises the controlled delay stages of a plurality of serial connections, and these are connected in series controlled delay stages and comprise the first controlled delay stages and the controlled delay stages of one or more follow-up serial connections.These each grades that are connected in series controlled delay stages all have the input that receives control signal, and this control signal is controlled the amount of delay that these described levels that are connected in series controlled delay stages produce.This first controlled delay stages receives reference clock signal from input unit, produces the first time-delay reference clock signal at output.In addition, these one or more follow-up controlled delay stages of serial connection receive the output signal that each is connected in series the last controlled delay stages of controlled delay stages, produce the further reference clock signal of time-delay according to this output signal.
Description of drawings
Reading will be understood objects and advantages of the present invention below in conjunction with the detailed description that accompanying drawing provides, in the accompanying drawing:
Fig. 1 is the diagram of the structure that is connected with multiple antialiasing filter of the A/D converter of the non-∑-Δ type in the prior art;
Fig. 2 is the diagram of structure of the A/D converter of the ∑-Δ type in the prior art;
Fig. 3 is the sequential chart of the clock demand of regular tap capacitor sigma-delta modulator;
Fig. 4 is the timing diagram of clock demand of the switched capacitor filters of improvement in performance, comprises two the leading phase clocks and first and second phase clocks;
Fig. 5 is the block diagram of a series of delay stages of clock of the generation switched capacitor sigma-Delta modulator of prior art;
Fig. 6 is the sequential chart of the signal that produces of this series delay stages of Fig. 5;
Fig. 7 is the more detailed block diagram of common delay stages;
Fig. 8 is a block diagram of eliminating the prior art of the variable cycle noise in the clock that will be provided as the reference clock of analogue-digital converter;
Fig. 9 is the block diagram of a most preferred embodiment of the equipment that comprises clock generator and sigma-delta modulator of the present invention;
Figure 10 is the more detailed block diagram of phase comparator that adopts in the present invention;
Figure 11 is the more detailed block diagram of the controlled delay stages that adopts in one embodiment of this invention.
Embodiment
Referring now to accompanying drawing, describe each feature of the present invention, part identical among the figure is denoted by the same reference numerals.
Referring now to Fig. 9, most preferred embodiment of the present invention is described.Switched capacitor sigma-Δ A/D converter 901 utilizes ordinary skill design, however, but because the cause of the P1 of phase clock very accurately that produces in such a way, P1e, P2, P2e, it can be with 13MHz or higher speed operation.In most preferred embodiment of the present invention, by the use ordinary skill, the variable cycle noise that for example utilizes phase-locked loop (PLL) 803 elimination meetings in being used as the noisy clock 801 of signal source, to occur, the quality of reference clock 805 is improved.Certainly, the application of phase-locked loop 803 is not a key of the present invention.Can adopt any technology that stable, jitter-free reference clock 805 is provided.
According to the present invention, 5 controlled delay stages 903-1,903-5 is connected in series, so when reference clock 805 is provided for the first controlled delay stages 903-1, just according to preceding four controlled delay stages 903-1, the priority of 903-4 output obtains clock signal (OUTD) 905-1 that one group of time-delay constantly increases ..., 905-4.The purpose of the 5th controlled delay stages 903-5 provides the load of the 4th controlled delay stages 903-4, and this load equals other 3 controlled delay stages 903-1 ..., each load of 903-3.The output of the 5th controlled delay stages 903-5 is not used.
Except that OUTD signal 905-x, most preferred embodiment of the present invention is by each controlled delay stages 903-1 ..., 903-5 also exports OUTQ signal 913-x and OUTQ
*Signal 915-x.OUTQ signal 913-x is numerically equal to OUTD signal 905-x.OUTQ
*Signal 915-x is the complement signal of OUTQ signal 913-x.Produce OUTQ and OUTQ
*The purpose of signal 913-x, 915-x is that they are offered logical circuit 907.Do like this and can load each OUTD signal 905-x in the same manner, so that each controlled delay stages 903-x will provide identical amount of delay basically, in most preferred embodiment, this amount of delay was 5 nanoseconds, so that make switched capacitor sigma-Δ A/D converter 901 carry out work with 13MHz.
Logical circuit 907 is OUTQ and OUTQ
*Signal 913-1 ..., 913-4,915-1 ..., 915-4 is for conversion into point-device phase clock P1, P1e, P2, P2e.According to well-known art designs logical circuit 907, so that produce phase clock P1, P1e, P2, the P2e that has suitable duty factor and time-delay each other.
In order to operate controlled delay stages 903-1 ... 903-5 obtains very little time-delay diffusion property, phase comparator 909 is incorporated in the design goes.Phase comparator 909 has two inputs.The first input end of phase comparator 909 receives first time delayed signal OUTQ, for example the OUTQ913-1 that is produced by the first controlled delay stages 903-1.Second input of phase comparator 909 receives second time delayed signal OUTQ, for example the OUTQ913-4 that is produced by the 4th controlled delay stages 903-4.The selection that offers these two time delayed signals of phase comparator 909 is the problem that depends on the design alternative of the specific design of phase comparator 909.Differ two bigger signals if be chosen in the phase place aspect, rather than select quite two signals near (promptly being delayed time on a small quantity), then phase comparator 909 just can easier design, and more accurate.In an alternate embodiment of the present invention, one of signal that offers phase comparator 909 is one of reference clock 805 rather than OUTQ signal 913-x.
Referring now to Figure 10, describe the operation of phase comparator 909, this figure is phase comparator 909 more detailed block diagrams.Phase comparator 909 is carried out two comparisons: at first, two delay clock signal OUTDx905-x and OUTDx+y905-(x+y) are provided for phase comparator 1001 corresponding first and second inputs.(as mentioned above, one of delay clock signal OUTD905 replacedly is a reference clock 805.) output of phase comparator 1001 is tested phase relation signals 1003.This tested phase relation signal 1003 is provided for the first input end of comparator 1005 then.Second input of comparator 1005 receives the reference signal 1007 of the required phase relation between expression these two delay clock signal OUTDx905-x, OUTDx+y905-(x+y).Pre-determine this required phase relation and represent the whole required time-delay that will between selected two delay clock signal OUTDx905-x, OUTDx+y905-(x+y), produce.
Referring again to Fig. 9, error signal 911 is provided for 5 controlled delay stages 903-1 now ..., the control input end of each of 903-5.The most preferred embodiment of one of these control delay stages 903-x (1≤x≤5) as shown in figure 11.The same with delay stages 503 shown in Figure 5, controlled delay stages 903-x comprises two inverter circuits 1101 that are connected in series, 1103, be controlled at and start and time-delay when closing second inverter circuit 1103 being provided with first capacitor 1105 between these two inverter circuits 1101,1103.Second capacitor 1111 is connected between the output and ground of second inverter 1103, is controlled at the time-delay when producing output signal OUTD905-x.In this most preferred embodiment of controlled delay stages 903-x, this embodiment is configured to an integrated circuit, and first and second capacitors 1105,1111 are realized with the P transistor that is connected in series between supply voltage VDD and ground and the form of the transistorized grid capacitance of n in this circuit.The use of this mode of grid capacitance is well known in the art, and is not described in detail in this.
The difference of controlled delay stages 903-x and delay stages 503 is that it also has two n transistors 1107,1109, respectively is connected between two inverter circuits 1101,1103 corresponding one and the ground.The error signal 911 that each grid receiving phase comparator 909 of n transistor 1107,1109 produces.By asserting error signal 911, just can control two capacitors 1105,1111 each discharge times, just dynamically controlled the amount of delay of between input lead 1113 and output signal OUTD905-x, introducing thus.
In an alternate embodiment, these two n transistors 1107,1109 can replace with the P transistor (not shown) that is connected between each inverter 1101,1103 and the supply voltage VDD.In this alternative structure, be to two capacitors 1105,1111 each charging interval rather than to controlling discharge time.Certainly, can also design and have charging and the n of discharge time and the transistorized delay stages of p that is used to control these two transistors 1105,1111.But, in the later case, will have to provide two input control voltages (each in n and p transistor), this can make the design of phase comparator 909 complicated more.
Except that said elements, exemplary delay stages 903-x also has the 3rd, the 4th and the 5th inverter circuit 1115,1117,1119.The 4th inverter circuit 1117 is connected with the output of second inverter circuit 1103, so that it can produce inversion signal OUTQ
*915-x.The output of the 4th inverter circuit 1117 also is connected with the input of the 5th inverter circuit 1119, and the 5th inverter circuit 1119 produces the noninverting signal OUTQ913-x that can offer logical circuit 907.Noninverting signal OUTQ913-x being provided rather than the reason of time-delay output signal OUTD 905-x is provided to logical circuit 907 is to guarantee at preceding four controlled delay stages 903-1, second inverter circuit 1103 in each of 903-4 is seen identical capacitive load, it is the input of next controlled delay stages 903-x, make these four controlled delay stages 903-1 thus,, it is minimum that the timing difference between the 903-4 reduces to.As will be described in more detail above, the 5th controlled delay stages 903-5 that is not used of its output just is used for providing uniform load to second inverter circuit 1103 of the 4th controlled delay stages 903-4.
In order to guarantee controlled delay stages 903-1, each first inverter circuit 1101 of 903-4 is also seen the identical capacitive load of seeing with the output of second inverter circuit 1103 of capacitive load, is provided with the 3rd inverter circuit 1115 in each controlled delay stages 903-x.In first given controlled delay stages 903-x, the 3rd inverter circuit 1115 is loads of first inverter circuit 1101, and first inverter circuit 1101 of next controlled delay stages 903-(x+1) is loads of second inverter circuit 1103 of this first given controlled delay stages 903-x.
The present invention is not subjected to the restriction of the application of controlled delay stages 903-x shown in Figure 11.On the contrary, those of ordinary skills understand the controlled delay stages that can also adopt other type.
Get back to Fig. 9 now, phase comparator 909 and controlled delay stages 903-1 as can be seen ..., 903-4 has constituted when reaching described phase relation together with the phase-locked loop that settles out.Because in this most preferred embodiment, this circuit is made into monolithic integrated circuit, so manufacturing process has guaranteed each controlled delay stages 903-1 ... the amount of delay that 903-5 introduces is identical basically, and the difference of each inter-stage has only several percentage points.Therefore, control amount of delay according to the measured value of two delay clock signal OUTDx905-x, OUTDx+y905-(x+y) and just guaranteed each controlled delay stages 903-1 basically ..., 903-5 produces required amount of delay.
So, these four time-delay clock 905-1 ... 905-4 have the tolerance limit strictness that produced than the common delay stages 503 that in prior art, is utilized for the sigma-delta modulator clocking the tolerance limit of Duoing.Because the cause of better tolerance limit, time-delay clock 905-1,905-4 can carry out work with higher speed (for example 13MHz and more than the 13MHz), and can still be provided for logical circuit 907 and produce phase clock P1, P1e, P2, P2e, do not have and make arbitrary time T 1, T2, T3, T4, T5 and T6 (see figure 4) accept short danger of duration than I.When design logic circuit 907, must note guaranteeing not introduce to have influence on phase clock P1, the Variable delay of the tolerance limit of P1e, P2, P2e.For example, in the design that realizes with the CMOS integrated circuit, must guarantee that whole output nodes of logical circuit 907 all have equal parasitic capacitance, so that make each phase clock P1, P1e, P2, P2e all have identical time-delay.In exemplary embodiments, replace OUTD signal 905-x to be provided for the independent signal OUTQ913-x and the OUTQ of logical circuit 907 by producing
*915-x has solved this problem, and these two signals only are used to produce the purpose of correct timing.Also have, as illustrated referring to Figure 11, the most preferred embodiment of one of controlled delay stages 903-x has guaranteed that the parasitic capacitance of intercaste is identical.
For a specific embodiment the present invention has been described.But those of ordinary skill in the art expects easily, can implement the present invention according to the ad hoc fashion different with the mode of above-mentioned most preferred embodiment.Do like this and can not break away from spirit of the present invention.For example, exemplary embodiments has been used 5 controlled delay stages 903-1 ... in fact 903-5 uses wherein preceding 4 and produces point-device phase clock P1, P1e, P2, P2e.But, the actual number of delay stages and to select those delay stages to come to be monitored by phase comparator 909 be the thing of design alternative.
Therefore, most preferred embodiment is illustrative, never should be counted as restrictive.Scope of invention determines that by appended claims rather than by above description interior all changes and the equivalent of category that drops on claims all covered by claims.
Claims (8)
1. equipment that comprises switched capacitor sigma-Delta modulator device comprises:
Receive the input unit of reference clock signal;
The controlled time-delay mechanism that is connected with this input unit, produce a plurality of time-delay reference clock signals according to the reference clock signal that is received; For each of a plurality of time-delay reference clock signals, corresponding amount of delay can be controlled by control signal;
With this input unit and the phase comparator device that is connected with this controlled time-delay mechanism, produce error signal, the size of this error signal is proportional to the tested phase relation between one of the reference clock signal that received and previously selected a plurality of time-delay reference clock signals and the bias of predetermined phase relation, this error signal is provided for this controlled time-delay mechanism, as each the control signal of amount of delay of a plurality of time-delay reference clock signals of control;
Produce the logic device of nonoverlapping first and second phase clock signals according to a plurality of time-delay reference clock signals; And
Described switched capacitor sigma-Delta modulator device comprises:
Receive the clock input unit of these nonoverlapping first and second phase clock signals;
The signal input apparatus of modulation signal is treated in reception; And
Comprise switched-capacitor circuit, this treats the device of modulation signal in the control modulated of these nonoverlapping first and second phase clock signals.
2. the equipment of claim 1, in this equipment:
First phase clock signal comprises the first leading phase clock signal and the first standard phase clock signal; And
Second phase clock signal comprises the second leading phase clock signal and the second standard phase clock signal.
3. the equipment of claim 1, controlled time-delay mechanism wherein comprises the controlled delay stages of a plurality of serial connections, these are connected in series controlled delay stages and comprise the first controlled delay stages and the controlled delay stages of one or more follow-up serial connections, in this equipment:
Each grade of the controlled delay stages of a plurality of serial connections all has the input that receives control signal, and this control signal is controlled the amount of delay that these described levels that are connected in series controlled delay stages produce;
This first controlled delay stages receives reference clock signal from input unit, produces the first time-delay reference clock signal at output; And
These one or more follow-up controlled delay stages of serial connection receive the output signal of the last controlled delay stages of the controlled delay stages of a plurality of serial connections, produce the further reference clock signal of time-delay according to this output signal.
4. the equipment of claim 1, wherein
Described phase comparator device produces error signal, and the size of this error signal is proportional to the tested phase relation between second chosen in advance time-delay reference clock signal of first chosen in advance time-delay reference clock signal of a plurality of time-delay reference clock signals and a plurality of time-delay reference clock signals and the bias of predetermined phase relation.
5. the equipment of claim 4, in this equipment:
First phase clock signal comprises the first leading phase clock signal and the first standard phase clock signal; And
Second phase clock signal comprises the second leading phase clock signal and the second standard phase clock signal.
6. the equipment of claim 4, controlled time-delay mechanism wherein comprises the controlled delay stages of a plurality of serial connections, these are connected in series controlled delay stages and comprise the first controlled delay stages and the controlled delay stages of one or more follow-up serial connections, in this equipment:
Each of the controlled delay stages of a plurality of serial connections all has the input that receives control signal, and this control signal is controlled the amount of delay that these described levels that are connected in series controlled delay stages produce;
This first controlled delay stages receives reference clock signal from input unit, produces the first time-delay reference clock signal at output; And
These one or more follow-up controlled delay stages of serial connection receive the output signal of last controlled delay stages, produce the further reference clock signal of time-delay according to this output signal.
7. the method for modulation signal in having the quick sigma-delta modulator of controlled clock generator may further comprise the steps:
Receive reference clock signal;
Utilize controlled time-delay mechanism to produce a plurality of time-delay reference clock signals according to the reference clock signal that is received;
Phase relation between one of the reference clock signal that measurement is received and previously selected a plurality of time-delay reference clock signals;
Should tested phase relation and predetermined phase relation make comparisons, and produce error signal according to comparative result;
Utilize this error signal to control the amount of delay that produces by this controlled time-delay mechanism, produce a plurality of time-delay reference clock signals thereafter then;
Produce nonoverlapping first and second phase clock signals according to these a plurality of time-delay reference clock signals thereafter;
Treating that modulation signal is applied to the signal input apparatus of switched capacitor sigma-Delta modulator device; And
This treats modulation signal in the control modulated of these nonoverlapping first and second phase clock signals to utilize this switched capacitor sigma-Delta modulator device.
8. the method for claim 7, wherein
Described phase relation is to measure between second chosen in advance time-delay reference clock signal of first chosen in advance time-delay reference clock signal of a plurality of time-delay reference clock signals and a plurality of time-delay reference clock signals.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US38940695A | 1995-02-16 | 1995-02-16 | |
| US08/389,406 | 1995-02-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1181163A CN1181163A (en) | 1998-05-06 |
| CN1093995C true CN1093995C (en) | 2002-11-06 |
Family
ID=23538133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96193112A Expired - Fee Related CN1093995C (en) | 1995-02-16 | 1996-02-16 | A fast sigma-delta modulator having controlled clock generator |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5796360A (en) |
| EP (1) | EP0809886A1 (en) |
| CN (1) | CN1093995C (en) |
| AU (1) | AU4852696A (en) |
| BR (1) | BR9607524A (en) |
| WO (1) | WO1996025795A1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10040422C2 (en) | 2000-08-18 | 2002-09-19 | Infineon Technologies Ag | Circuit arrangement and method in switched operational amplifier technology |
| JP3622685B2 (en) * | 2000-10-19 | 2005-02-23 | セイコーエプソン株式会社 | Sampling clock generation circuit, data transfer control device, and electronic device |
| CN1792038B (en) * | 2003-05-21 | 2010-06-16 | 模拟设备股份有限公司 | Sigma-delta modulator and sigma-delta modulation method |
| GB0411884D0 (en) * | 2004-05-28 | 2004-06-30 | Koninkl Philips Electronics Nv | Bitstream controlled reference signal generation for a sigma-delta modulator |
| US7612595B2 (en) * | 2006-09-19 | 2009-11-03 | Melexis Tessenderlo Nv | Sequence independent non-overlapping digital signal generator with programmable delay |
| CN101867376B (en) * | 2009-04-17 | 2014-08-27 | 苏州亮智科技有限公司 | Clock synchronous circuit |
| JP4864145B2 (en) * | 2010-01-08 | 2012-02-01 | 富士通株式会社 | A / D converter and D / A converter |
| CN106411296A (en) * | 2015-07-30 | 2017-02-15 | 深圳市中兴微电子技术有限公司 | Clock time-delay circuit |
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| US5146121A (en) * | 1991-10-24 | 1992-09-08 | Northern Telecom Limited | Signal delay apparatus employing a phase locked loop |
| US5150068A (en) * | 1988-08-10 | 1992-09-22 | Hitachi, Ltd. | Clock signal supply method and system |
| EP0609967A2 (en) * | 1990-06-29 | 1994-08-10 | Analog Devices, Inc. | Apparatus for detecting phase errors |
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|---|---|---|---|---|
| US5184027A (en) * | 1987-03-20 | 1993-02-02 | Hitachi, Ltd. | Clock signal supply system |
| DE3876979D1 (en) * | 1988-03-31 | 1993-02-04 | Itt Ind Gmbh Deutsche | CIRCUIT ARRANGEMENT FOR AVERAGE VALUE FOR PULSE DENSITY D / A OR A / D CONVERSION. |
| US5087829A (en) * | 1988-12-07 | 1992-02-11 | Hitachi, Ltd. | High speed clock distribution system |
| US5055843A (en) * | 1990-01-31 | 1991-10-08 | Analog Devices, Inc. | Sigma delta modulator with distributed prefiltering and feedback |
| JPH05505287A (en) * | 1990-01-31 | 1993-08-05 | アナログ・ディバイセス・インコーポレーテッド | sigma delta modulator |
| KR920018771A (en) * | 1991-03-29 | 1992-10-22 | 가나이 쯔또무 | Semiconductor Integrated Circuits & Data Processing Processors |
| US5140325A (en) * | 1991-05-14 | 1992-08-18 | Industrial Technology Research Institute | Sigma-delta analog-to-digital converters based on switched-capacitor differentiators and delays |
| US5436939A (en) * | 1992-05-06 | 1995-07-25 | 3 Com Corporation | Multi-phase clock generator and multiplier |
| US5349352A (en) * | 1992-12-21 | 1994-09-20 | Harris Corporation | Analog-to-digital converter having high AC line noise rejection and insensitive to AC line frequency variations |
| US5398263A (en) * | 1993-01-14 | 1995-03-14 | Motorola, Inc. | Autonomous pulse train timing controls for time-mark alignment |
| US5313205A (en) * | 1993-04-06 | 1994-05-17 | Analog Devices, Inc. | Method for varying the interpolation ratio of a digital oversampling digital-to-analog converter system and apparatus therefor |
| US5408235A (en) * | 1994-03-07 | 1995-04-18 | Intel Corporation | Second order Sigma-Delta based analog to digital converter having superior analog components and having a programmable comb filter coupled to the digital signal processor |
-
1996
- 1996-02-16 AU AU48526/96A patent/AU4852696A/en not_active Abandoned
- 1996-02-16 BR BR9607524A patent/BR9607524A/en not_active IP Right Cessation
- 1996-02-16 WO PCT/SE1996/000214 patent/WO1996025795A1/en not_active Application Discontinuation
- 1996-02-16 EP EP96904410A patent/EP0809886A1/en not_active Ceased
- 1996-02-16 CN CN96193112A patent/CN1093995C/en not_active Expired - Fee Related
-
1997
- 1997-04-14 US US08/840,172 patent/US5796360A/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5150068A (en) * | 1988-08-10 | 1992-09-22 | Hitachi, Ltd. | Clock signal supply method and system |
| EP0609967A2 (en) * | 1990-06-29 | 1994-08-10 | Analog Devices, Inc. | Apparatus for detecting phase errors |
| US5146121A (en) * | 1991-10-24 | 1992-09-08 | Northern Telecom Limited | Signal delay apparatus employing a phase locked loop |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0809886A1 (en) | 1997-12-03 |
| AU4852696A (en) | 1996-09-04 |
| CN1181163A (en) | 1998-05-06 |
| WO1996025795A1 (en) | 1996-08-22 |
| BR9607524A (en) | 1997-12-30 |
| US5796360A (en) | 1998-08-18 |
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