SU1324113A1 - Current-to-pulse repetition frequency converter - Google Patents

Abstract

The invention relates to a pulse technique. The purpose of the invention is to improve the accuracy of the conversion. The converter contains integrator 1, comparator 4, RS flip-flop 5 and current key 8. Increasing the clock frequency of the generator 7 by praz and using the frequency divider 6 by n reduces the maximum delay between the time the comparator 4 operates and 1 or . . (L

Description

The invention relates to a pulse technique and can be used in current-frequency converters.

The aim of the invention is to improve the conversion accuracy.

The drawing shows a functional diagram of a current to pulse frequency converter.

The current-to-pulse frequency converter contains integrator 1, made on operational amplifier 2 with capacitor 3 in the feedback circuit, comparator 4, RS-trigger 5, frequency divider b, oscillator 7 clock frequency, control current switch O, first The first 9 and second 10 input buses and the output bus 11.

The input bus 9 of the converter is connected to the first input of the integrator 1, the output of which through the comparator 4 is connected to the S input of the RS trigger 5, the direct output of which is connected to the installation input of the divider 6, the counting input of which is connected to the output of the generator 7 and the output is connected to the inverse R-input of the RS-flip-flop 5 and the controlled input of the current switch 8, the output of which is connected to the second input of the integrator 1, and the input is connected to the second input bus 1 of the converter. The output of the converter is the direct output of the RS flip-flop 5.

The converter works as follows.

Let us assume that the RS-flip-flop 5 is in the zero state. In this case, the frequency divider 6 and the current key 8 are in the off state. The input current through the bus 10 is fed to the input of the integrator 1 and charges the capacitor 3. When the voltage at the output of the integrator 1 reaches the response value of the comparator 4, the latter switches the RS flip-flop 5 to one and enables the frequency divider 6 to work.

Divider 6 is implemented on the basis of a subtraction counter, the counting input of which is connected to the output of the generator 7, and the output is the output of the higher bit.

The use of a frequency divider and a generator of the increased frequency allows to reduce the time delay between the instant of operation of the comparator and the moment of switching on the current key and, consequently, reduce the error of the nonlinearity of the conversion

while maintaining the frequency characteristics of the integrator and the current key.

When the first pulse arrives from the output of the generator 7, the high-order bit of the frequency divider 6 connected to the controlled input of the current switch 8 switches to the unit state. In this case, the output of the reference current source supplied to the input bus 10 is connected to the second input of the integrator 1 and the capacitor 3 begins to discharge. The discharge of the capacitor lasts until the frequency divider counts n pulses (n is the division factor of the divider),

On the nth pulse, the high-order splitter switches to the logical zero state, turns off the current switch, and sets the RS flip-flop to the zero state. Next, the conversion process is repeated as described.

x

Increasing the clock frequency of the generator by n times and using a frequency divider by n will reduce the maximum delay between the time the comparator operates and the time when the current switch is turned on and, consequently, reduce the conversion error.

Claims (1)

Invention Formula The current-to-pulse frequency converter, containing an integrator, the output of which is connected to the comparator input, a current switch and a trigger, the output of which is connected to the output bus, the first input bus connected to the first integrator input, characterized in that it is additionally entered a clock frequency generator and a frequency selector, the comparator output being connected, to the S input of a trigger, whose direct output is connected to the installation input of a frequency divider whose counting input is You are a course to dklyuchen oscillator clock frequency, significant bit of the frequency divider is connected to the inverted R-input of the flip-flop and a controllable current input key signal input of which is connected to a second input bus and the output current switch coupled to a second input of the integrator.