SU1515336A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering and can be used as a master oscillator. The purpose of the invention is to expand the range of output frequencies. The goal is achieved by introducing into the digital frequency synthesizer a multiplier of 3 codes, an adder of 6 codes, a memory register 7, a frequency divider 10 with a variable division factor, a decoder 11 and a shift register 13. The divider 10 divides the output frequency of the comparator 9 by 2 ^N times and thus the specified output range with an arbitrary overlap is realized. The divider 10 is triggered precisely from the leading edge of the input pulse. 1 hp f-ly, 2 ill.

Description

ate

SP

Ltd

05

(puff.i

can be used in radio receivers and radio transmitters of various devices as a given oscillator.

the uniform hypothetical output frequency sequence (fig. 2b) is rewritten from NS 4 to register 5.

The aim of the invention is to expand the peculiarity of the work of any synthesizer

ten

the frequency performed on the basis of the accumulating adder consists in the fact that the NS separates the nearest pulse after the hypothetical and the code L {contains information about the delay of the real pulse relative to the hypothetical. It is physically impossible to realize a shift of the selected pulse towards

Oenche range of output frequencies.

Figure 1 shows a structural electrical circuit of a digital frequency synthesizer; 2 shows timing diagrams for his work.

The digital frequency synthesizer (Fig. 1) contains the frequency generator 1, the frequency code setting unit 2, the multiplier 3 codes accumulating the advance adder 15, therefore using the sum- (NS) 4, the first register 5 of the memory, the adder 6 calculates time error matrix 6 codes, second memory register 7, digital-to-analog converter (D / A converter) 8, comparator 9, frequency divider 10 with variable de-20 laziness coefficient (LCPD), decoder 11, linear voltage generator (clay) and the shift register 13.

The generator 12 of the linearly varying voltage (Fig. 1) includes the control-25 at the clock input of the second register, the 7th current generator 1 (CBS), control- and recording, the code P ... This key is 15 and the capacitor 1b .

previous pulse output generator 1.

R ; M - J; .

Register 13 counts t, generator 1 pulses (in Fig. 2), after which at its first output a pulse (Fig. 2d) arrives

and writing the code into it, j code, is fed to the input of the DAC 8, at the output of which a voltage proportional to P begins to set; (on 3Q fige solid line). The time to establish the voltage should not exceed the digital frequency synthesizer works as follows.

35

The binary code M of the output frequency fgji from the output of block 2 is fed to the jammer 3 and to the decoder 11. The decoder 11 searches for the highest unit n of the binary code M of the output frequency and generates at its output a code of the number n expressing the number of bits (start from the highest bit to the first logical unit. A code of the number n is fed to the input of the multiplier 3 and to the input of the control 40 of the PDCK 10. At the output of the multiplier 3, a code is formed, in the high order of which a logical unit is always present.

The 2 M code is fed to the discharge input of the NS, to the input of the adder 6 and to the input of the control CLINE 12.

With the pulse frequency at the output of the generator 1 (Fig. 2a) in

and writing the code into it, j, the code is fed to the input of the DAC 8, the output of which begins to establish a voltage proportional to P; (on 3Q fige solid line). The time for establishing the voltage should not exceed n-T ,, where TO is the period of the pulse of the generator 1.

At the same time, the register 13 counts another t pulses (on fig.2d), and at its second output a pulse appears that triggers GLIN 12. Up until this point, GLIN 12 was in the following state. The control input IGT I t receives a code, at the output of UGT k a current proportional to this code is set:

I 1, 2

M,

45

where 1 - current, UGT And with a minimum

control code (logical unit only in the lower order). For this output frequency

The output of the UGT 1 + is constant, i.e. it does not depend that the HC, having a capacity of N, carries out -50 on the time. The control key is 15 seconds, the accumulation of the accumulated number is numerical, and the capacitor 1b is discharged, so is the scrap M. After k periods of the output clock, as the output of GLINE 12 is grounded, the oscillator of the generator 1 overflows the NS and at its output the pulse from the second output of the register 13 an impulse appears on the control input of the ups (fig. 2b), a post-55 equal key 15 and closes it for the time of its own. Starts- and on the information input of the register 13. with the charge of the capacitor 1b current I (on

On the impulse, the information J on the error of the time position i-ro and the uniform hypothetical sequence of the output frequency (Fig. 2b) is rewritten from NS 4 to register 5.

ten

the frequency, made on the basis of the accumulating adder, is that the NS separates the nearest pulse after the hypothetical and the code L {contains information about the delay of the real pulse relative to the hypothetical. It is physically impossible to realize a shift of the selected pulse towards

15 advance, so a time error of 20

advance, so a time error is calculated using the sum 6

on the clock input of the second register 7 and recording, in it the code R .. This

previous pulse output generator 1.

R ; M - J; .

Register 13 counts t, generator 1 pulses (in Fig. 2), after which a pulse appears on its first output (Fig. 2d), arriving

25 to the clock input of the second register 7 and recording, in it the code R .. This

40

and writing the code into it, j, the code is fed to the input of the DAC 8, the output of which begins to establish a voltage proportional to P; (on 3Q fige solid line). The voltage setting time must not exceed

Shat T - T, where TO is the period of the pulse of the generator 1.

At the same time, the register 13 counts another t pulses (on fig.2d), and at its second output a pulse appears that triggers GLIN 12. Up until this point, GLIN 12 was in the following state. The control input IGT I t receives a code, at the output of UGT k a current proportional to this code is set:

I 1, 2

M,

where 1 - current, UGT And with a minimum

control code (logical unit only in the lower order). For this output frequency

The output of the UGT 1 + is constant, i.e. not dependent on time. The control key 15 is open, and the capacitor 1b is discharged, since the output of CLAY 12 is grounded,

The impulse from the second output of the register 13 is fed to the control input of the ffig (.2e dotted line). At that moment, when the voltage across the capacitor

l6 will reach a value equal to the voltage at the output 1 | LP 8 (in FIG. 2 e, the intersection of solid and dashed li-

ny), at the output of the comparator 9 is formed - - .., there is a difference (Fig. 2g). It can be shown that, with the purpose of an expander, the other input of which is matched with the generator voltage of a linearly varying voltage, can be installed on the frequency code setting unit, and the time delay of this differential relative to the pulses at the generator output 1 is inversely proportional to the code and directly proportional to the magnitude of the temporal error R., which must be established. To do this, we define the point in time at which the voltages at inputs 9 will take equal values;

M

comparator

h tl

1 2

where C

and"

 ,

capacitor capacitance 1b; the voltage at the output of the DAC 8 with a minimum control code (logical unit only in the lower order).

At the choice of size of capacity With

IO / U.-T,

,, - - PI,

about

and in the ideal case, full compensation of the phase modulation of the pulses is carried out.

At the next HC overflow, the entire cycle is repeated. The difference lies in a different value of I and, therefore, in a different voltage at the output of the DAC 8, determined by the new number P. . At the output of the comparator 9, a pulse sequence is formed with a frequency (,) with a uniformly spaced (front leading edge. DDC 10 divides the output mass

comparator 9 is 2 times, and thus the specified output range is implemented with an arbitrary overlap. DPKD 10 should be triggered precisely from the leading edge of the input pulse.

Claims (2)

1. A digital frequency synthesizer containing a serially connected reference frequency oscillator, accumulating adder and the first memory register, the clock input of which is connected to the transfer output of accumulating adder, serially connected digital-55 is an oscillator starting input analog converter and comparatively varying .. 2. A synthesizer in accordance with claim 1, which is based on the fact that the generator of linearly varying voltage holds the controlled current generator, the output of which is connected to the signal input of the controlled key and one output of the capacitor, the running key of the controlled key and The other output of the capacitor is connected to a common PCB digital frequency :, where the control input and the output of the controllable current generator are the corresponding control input and the output of the ramp voltage control input of the controllable voltage switch. KG)  - .., u and with the fact that, with the purpose of an extender, the other input of which is matched with the generator voltage of a linearly varying voltage, is required for the frequency code setting block, 0 five 0 five 0 five 0 five 0 5 is the input of the start of the generator linearly varying m .. nor the output frequency range, a serially connected decoder, a code multiplier, a code adder and a second memory register, the output of which is connected to the input of a digital-analog converter, as well as a shift register and a frequency divider with a variable division factor, a clock input of which is connected with the output of the comparator, another input of the code adder is connected to the output of the first memory register, the output of the frequency code setting unit is connected to the input of the decoder and another input of the code multiplier, the output of which is Also, with a discharge input of the accumulating adder and a control input of the generator of a linearly varying voltage, the output of the reference frequency generator is also connected to the clock input of the shift register, whose information input is connected to the transfer output of the accumulating adder, the first and second outputs of the shift register are connected respectively to the clock the input of the second memory register and the start-up input of the generator of linearly varying voltage; the output of the decoder is connected to the control input of the frequency divider with variable oeffitsientom divider whose output is the output of the digital frequency synthesizer. 2. The synthesizer of claim 1, wherein the linear variable voltage generator comprises a controlled current generator, the output of which is connected to the signal input of the controlled key and one output of the capacitor, the course of the controlled key and the other the output of the capacitor is connected to a common digital breeder digital frequency changer; the control input and the output of the controlled current generator are respectively the control input and the output of the linearly varying voltage generator, and the control input of the adjustable key KG) M 0. to - I I I I 1 I - I J j. I.I I CHN (rtsg.2