SU1306450A1 - Phase locking device - Google Patents

Abstract

The invention relates to a pulse technique. The purpose of the invention is to expand the functionality by expanding the range of operating frequencies and the duration of the phasing signals and signals of the master. The device contains master 1, delay line 2, memory block 3, switch 5. The decoder 4 and the one-shot 6 are newly introduced. Switch 5 consists of a multiplexer, an IC element - KEY OR, I. mtf 3 Il. 00 о а 4 СП

Description

The invention relates to a pulse technique, namely, devices for generating reference pulse sequences with automatic phase correction with respect to the input synchronization signal, and can be used for generating control pulses of sequences in correlation processing devices of radar information, precision paths for measuring distance and in sync generators of digital information transmission equipment.

The purpose of the invention is to expand the functionality by expanding the range of operating frequencies and durations of the phasing signals and the signals of the master oscillator.

FIG. I presents the structure-electrical diagram of the phase synchronization device; in fig. 2 shows an embodiment of the switch; Fig. 3 shows timing diagrams explaining the operation of the device.

The phase synchronization device contains a generator 1, a delay line 2, a memory block 3, a decoder 4, a switch 5 and a one-shot

b, and the multiplexer 7, the element EXCLUSIVE OR 8 and the element AND 9 are part of the switch.

The phase synchronization device operates as follows.

The master oscillator 1 generates a digital sequence of pulses, and the delay line 2 generates a series of reference sequences of pulses. The phase shift between the reference pulse sequences is determined by the delay time between adjacent delays of the delay line. When the number of taps of the delay line 2 is equal to n, (n + l) realizations of the reference pulse sequence are formed (Fig. 3a,

c, d, d, e, g) at. The phasing signal (fig. 3b), arriving at time t, to the synchronization input of memory block 3, fixes its leading edge (difference from O to 1) to the (n + 1) outputs of memory block 3, the state of logical levels, present at this moment in time at the corresponding taps of the delay line 2 (cM |, „fig. 3, 3, and, k, l, m, n),

(n + 1) -Discharge positional code at the output of the memory block 3 corresponds to the phase shift of the phasing signal relative to the reference sequence of the master oscillator J. Decipher

A 4 (n + 1) -discharge position code is decrypted into an n-DIFFERENT BINARY code, where m logjn + 3, and CO is the nearest lower integer value.

The switch 5, in accordance with the control codes received from the decoder 4, passes one of (n + 1) reference pulse sequences to the device output, and the reference sequence in which the level difference from 1 to O has a lead over the positive the front of the phasing pulse is not more than it (Fig, 3, g).

Due to the final decoding time of the code in decoder 4 at the output of switch 5, the correct reference sequence of pulses is established after the time € (Fig. 3, o). To eliminate the appearance of spurious pulses, a single vibrator 6 is provided at the output, which forms a blanking pin (Fig , 3, p) on the leading edge of the phasing signal. The blanking signal arrives at the building input of switch 5 and prohibits the passage of information to the device output at the time the decoder 4 switches and sets the device output level O, which coincides with the level of the beginning phase of the selected reference sequence. The duration of the blancier of the impulse t, must be not less than the decryption time cTg.

The falling edge of the blazing pulse, in order to eliminate the appearance of spurious pulses at the device output, must be in the zero phase interval of the selected reference sequence.

Into devices; the possibility of inverting the corresponding BjnoEpix reference sequences is provided, which is provided by the switch 5, an embodiment of which is shown in FIG. 2. This binds not only to the (n +) main reference pulse sequence, but also to the (n + l) inverted the reference pulse sequence, which allows you to get twice the number of reference signals without increasing the number of taps and lengthening the delay line 2. In switch 5, the output of multiplexer 7 is connected to the first input of the SES | CHAUV | EE or 8, which performs logical

modulo 2 addition operation. Depending on the logic level, at the second input of the element, EXCLUDING IT OR 8, the output of this element appears-,. with the multiplexer 7 selected, the reference pulse train in the forward or inverse form. When level-. not O at the second input of the EXCLUSIVE OR 8 element is provided about Q the walking of the selected reference pulse sequence in the normal form, and level 1 leads to the inversion of the selected reference sequence.

In connection with the final decryption time in decoder 4, an uncertainty condition is observed at the fg interval at the output of multiplexer 7 and the element EXCLUSIVE OR 8. The one-way oscillator 6 prohibits the passage through the And 9 element of the reference pulse train until the completion of the transient processes.

F o rmula of the invention

1. A phase synchronization device containing a series-connected master oscillator and a delay line, whose input and its taps are connected to the corresponding information. Q 5

about

five

0

the onboard inputs of the switch, as well as the memory block, the synchronization input of which is the input of the device phase signal, characterized in that, with the aim of extending the functionality by expanding the range of working frequencies and phase distance signals and. signals of the master oscillator, a descrambler and a one-shot are entered, the input and five taps of the delay line through the serially connected memory block and the decoder are connected to the m control inputs of the switch, to the gate input of which the output of the one-shot is combined, the input of which is combined with the clock synchronization input memory, with the switch output being the device output. 2. The device according to claim 1, characterized in that the switch is designed as a series-connected multiplexer, an EXCLUSIVE OR element and an AND element, and n + 1 multiplexer inputs are information inputs, (ml) multiplexer inputs and a second input of an EXCLUSIVE OR element the control inputs, the second input and output of the I element - the gate input and output of the switch.

1

Claims (2)

Claim 1, a Phase synchronization device containing a serially connected master oscillator and a delay line, the input and η of the taps of which are connected to the corresponding information inputs of the switch, as well as a memory unit, the synchronization input of which is an input of the phasing signal of the device, characterized in that, in order to expand the functional possibilities by expanding the range of operating frequencies and durations of phasing signals and signals of the master oscillator, a decoder and a single vibrator are introduced, while the input and η tap The delay lines are connected through a series-connected memory block and a decoder to the m control inputs of the switch, to the gate input of which a single-vibrator output is connected, the input of which is combined with the synchronization input of the memory block, the output of the switch being the output of the device, 2. The device pop. 1, characterized in that the switch is made in the form of a series-connected multiplexer, an EXCLUSIVE OR element and an AND element, with n + 1 inputs of the multiplexer being information inputs, (w-1) inputs of the multiplexer and the second input of the EXCLUSIVE OR element - control inputs, the second input and the output of the element And - the gate input and output of the switch. t 0 1 I 1 al_L 12 3 4 56 I ’I ___ 1 ___ 1—1 1 c? -Ct Fig.Z