SU1305639A1 - Function interpolator - Google Patents

Abstract

The invention relates to numerical control and can be used in automatic systems of thread-cutting, gear-cutting and winding machines, as well as robots serving conveyors and production lines. The aim of the invention is to increase the speed of the interpolator. The functional interpolator contains the register of the leading coordinate 1, the control unit 10, the pulse counter 13, the elements 11 and 12, and for each coordinate entered the register 2, the switches 3, 4, 9, the adder 5, the pulse driver 7, the decoder 6, the element OR 8. The main feature of this device is the principle of functional interpolation implemented in it, in contrast to the pulsed (step-by-step) nature of information exchange. A procession to the processing of bursts of pulses (words) instead of single pulses (bits) allows to significantly increase the speed of an interpolator implemented on the basis of standard blocks. In addition, the invention makes it possible to increase interpolation accuracy by organizing the control in a function of the actual (and not specified) motion of the leading coordinate. 2 Il. 5 pk O) D5

Description

The invention relates to numerical program control and can be used in automatic systems for thread-cutting, gear-cutting and winding machines, as well as robots serving conveyors and production lines.

The purpose of the invention is to increase the speed of the interpolator.

Figure 1 shows a diagram of a functional interpolator; figure 2 - timing diagrams.

The main feature of the interpolator is the code-based principle of functional interpolation implemented in it, unlike the well-known impulsive (step-by-step) character of information exchange. The transition to the processing of bursts of pulses (words) instead of single pulses (bits) allows us to increase the interaction between the interpolator implemented on the basis of standard blocks.

Functional interpolator (figure 1 contains the register I leading coordinates, serially connected in each slave coordinate register 2, the first switch 3, the third switch 4, the adder 5, the decoder 6, the driver 7 pulses, the element OR 8 second. Switch 9, block 10 control, the second and first elements And 1 and 12, the pulse counter 13, the control unit 10, consisting of the console 14, the frame counter 15 and the memory block 16.

The interpolator works as follows.

When power is applied to the interpolator, switches 3 and 4 are connected to adders 5, registers 1 and 2, and pulse counters 13 and frames 15 are zeroed. The zero counter code of 15 frames is fed to the address inputs of the memory block 16 in the control block 10. The zero pulse of the pulse counter 13 is fed to the write inputs of the registers 1 and 2 and the pulse counter 13 pulses, allowing the data in them to be located at the address O of the memory block 16, i.e. . an overlap in the frame along the leading coordinate AZj, in the forward code, 13 pulses are recorded in the register and counter, and increments are in the slave coordinates iHd, in the additional code - in the corresponding registers 2. The increment information is carried by (n-1) lower-order Dov data block 16 memory. Older bits d) and uY are significant and are served on pack5.

the equal inputs of the corresponding switch keys 9, and the most significant bit D Z controls the AND 12 element at its inverse input. If the zero frame corresponds to zero information (dX uY uZ 0), the result of the addition in adders 5 is zero. In this case, the single potentials from the outputs of the decoder 6 are supplied through the elements OR 8 to the first inputs of the element 12, after which the decoding in the decoder 6 is interrupted.

After pressing the Start button on the remote control 14 of the control unit 10, the leading Z coordinate is started (for example, a screw-cutting spindle or a table milling machine), power is supplied to the slave X, Y coordinates, the unit potential arrives

0 to the input element And 11, opening it, and. signal 1 passes to the input of the element I I2 and to the input of the countdown of the counter 13 pulses. When a negative code -1 pulses appear in the counter 13, a pulse is generated at its output, which arrives at the counting input of the counter 15 frames, setting the address of the first frame, and at the write inputs of registers 1 and 2 and the counter 13 pulses. Information about the increments LХ, & Y, (iZ, in the first frame from the lower bits of the memory block 16 is entered into the corresponding registers I and 2 and the counter 13 pulses.

5 depending on the information of the higher bits (О or 1) of the codes хХ, iY, the switch 9 connects the interpolator outputs to the positive or negative inputs of the corresponding coordinates. The highest bit of the fiZ code, equal to zero in all frames, goes to the inverse input of the element And 12. The results of adding DF and UZ ,, uY, and UZ, are ready for transmission to the inputs

S corresponds to 5x decoders 6, but they are not analyzed by the control signal.

The first impulse of testing from the leading coordinate Z ;, passage through

0 element 12, allows the transfer of the results of the addition to the outputs of adders 5, and then decoding in blocks 6. If the result of summing the direct code uZ with the additional code uX (uY) turns out to be positive, the output potential of the decoder 6 establishes a single potential, which the element OR 8 goes to the input

0

element And 11, and the switch D switches the outputs of the adder 5 with the outputs of the register 2 to the outputs of the adder 5.

If the summation result is negative, a single potential is set at the output of the decoder 6. The pulse of the pulse shaper 7 is fed through the switch 9 to the slave coordinate X (Y) and switches the switch 3 of the inputs of the adder 5 from the outputs of the register 2 to the outputs of this adder. Upon completion of the pulse of the imaging unit 7, the decoder 6 analyzes the result of the addition of the previous negative sum with the uZ codes. If the result is again negative, another impulse is given to the driven coordinate X (Y), and the new amount is added to UZ. The cycle continues until the result in the adder 5 is no longer negative,

but its duration in any case does not exceed the period of the pulse.

Whenever all decoders 6 register the presence of non-negative codes in all adders 5, the first element 11 opens, preparing the second element 12 to pass

the next pulse Zj, and decreasing to the information inputs of the pulse counter, as well as the first and second elements AND, characterized in that, in order to increase speed, the register of the leading

gist, first switch, adder, decoder, pulse driver and second switch, as well as element

the counter code is one unit. Subsequent impulses for testing the master drive Zj initiate a repetition of the considered cycle.

If, as a result of the next dictation, the coordinates and each slave coordinate of interpolation nullify the nat of the counters connected to the 13 pulses, the pulse from its output will increase the frame number in the counter of 15 frames by one and allow entering the information of the next frame 40. OR and the third switch, moreover, the registers 1 and 2 and the counter 13 pulse of the adder are connected to the second owls. With the advent of pulses Z; the processing by the inputs of the first and with the first inputs will continue. After testing the third switch, the second input of the last frame of the older program is connected to the output of the register a number of code & Z becomes equal to one 45 leading coordinates, the output - with the second niche. The presence of this signal at the input of the adder, and the control input-inverse input of the I 12 prep element, with the second output of the decoder, also influences the passage of the Z pulses; . By the input of the element OR, the second input of the completion of the program is terminated. For which it is connected to the third output of the termination of testing in arbitrary 50 of the decoder and to the second input of the time required to remove the signal, the second output of which is connected to the first control input of the adder and the decoder, the second control input of the adder is connected to the 55 output of the first the element And the second control unit input of the decoder, the first input of the first element I is connected to the first input of the functional inn using the Start button of the remote control 14 in the unit

10 controls.

The timing diagram of the testing program (figure 2) consists of three frames: I frame LC 3, uY 4,

11kadr LH 8, III frame,., D.

o

five

On the first pulse Z, in the adder of the X coordinate, the operation O is carried out; in the adder, the coordinate Y is 5-4 I O. On the second impulse Z; in the accumulator X O and the pulse X- is sent, then. In the accumulator Y 1-4 -3 O and the pulse Y is sent; , then 0. On the third pulse Z in the adder X D - 3 1 O, in the adder Y 2-4 -2: O and the second pulse Y is sent; then O. According to the fourth pulse Z, in the adder X “Оn the second pulse X; , then O, In the adder Y 2-4 -1 - i О and the third pulse Y, then O. On the p impulse Z; adder X and the third pulse X. In the adder Y and the fourth 0 pulse Y; . The pulse counter 13 is zeroed and the frame is changed.

Other frames are processed in the same way.

the invention

Formula

The functional interpolator containing the control unit, the outputs (n-1) of which bits are connected

pulses, as well as the first and second elements AND, characterized in that, in order to increase speed, the register of the leading

gist, first switch, adder, decoder, pulse driver and second switch, as well as element

coordinates and each slave coordinate are serially connected RE-OR and a third switch, with the outputs of the adder connected to the second inputs of the first and the first inputs of the third switch, the second input of which is connected to the output of the register of the leading coordinate, the output to the second input of the adder and the control input with the second output of the decoder and the first input of the OR element, the second input of which is connected to the third output of the decoder and to the second input of the former, the second output of which is connected to the first control input Ummator and decoder, the second control input of the adder is connected to the output of the first element AND and the second control input of the decoder, the first input of the first element And is connected to the first input of the functional interpolator, the second input - with the output of the second element And and the counting input of the pulse counter, the input of the pulse counter is connected to the register entry input, the output of the pulse counter and the input of the control unit, the outputs of which bits are connected to the control input of the second switch and the inverse input of the first AND means, data inputs of the register and the leading coordinates reRedaktor N.Rogulich

Compiled by And, Shvets Tehred L. Serdyukova

Order 1426/44 Circulation 864 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, F-33, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

056396

the gistors in each slave coordinate are connected to the information inputs of the pulse counter and the outputs (p-1) of the bits of the control unit, the first

 the input of the second element And is connected to

the control output of the control unit, and the second inputs - with the outputs of the element OR of each slave coordinate :, the control input of the first switch fO is connected to the first output of the decoder.

FIG. g

Corrector I. Muska

Claims (1)

Claim A functional interpolator containing a control unit, the outputs (η-l) of the discharges of which are connected to the information inputs of the pulse counter, as well as the first and second elements of I, characterized in that, in order to improve performance, a register of the leading coordinate is introduced into each guided coordinate in series connected register ^ first switch, adder, decoder, pulse shaper and second switch, as well as an OR element and a third switch, and the outputs of the adder are connected to the second inputs of the first and first inputs and a third switch, the second input of which is connected to the output of the leading coordinate register, the output is connected to the second input of the adder, and the control input is the second output of the decoder and the first input of the OR element, the second input of which is connected to the third output of the decoder and to the second input of the shaper, the second output of which connected to the first control input of the adder and the decoder, the second control input of the adder is connected to the output of the first element And and the second control input of the decoder, the first input of the first element And is connected to the first input of the functional interpolator, the second input is with the output of the second AND element and the input of the countdown counter of the pulse counter, the input of the pulse counter record is connected to the register recording input, the pulse counter output and the input of the control unit, the outputs of which η discharges are connected to the control input of the second switch and the inverse input of the first element And, the information inputs of the register leading coordinates and 1305639 6 histres in each slave coordinate are connected to the information inputs of the pulse counter and outputs (p-1) of the bits of the control unit, the first 5 input of the second AND element is connected to the control output of the control unit, and the second inputs to the outputs of the OR element of each slave coordinate the input of the first switch 10 is connected to the first output of the decoder. r I 'U0 d = o 70' —Ϊ— ‘ I I I G 1 ΠΊ 1 P 1 N 0 t P fl PP t gpp p p p 1 1 1 Euli Jl ✓ Ϋ < Hi Z _t z0 = 0 70 W g Ί - P ppg P P ΊΠ G “~ T. P and pl ............ l Fri hl 1ΓΣΞΞΣΣΣΣ — J 1. L f ΓΊΠΠΓΊΠ i | q iinQqr II ^x Γ ΓΞΞΙ: zz Figure 2