SU1298720A2 - Device for localizing failures in digital circuits - Google Patents

Abstract

This invention relates to automation and computing. The purpose of the invention is to improve the reliability of the results of operation of the device is achieved by the fact that in the device containing the adder 1 modulo two, the shift register 2, the trigger 3, the block 4 matches, the elements OR 7 and HE 9 and two formers 6 and 8 short pulses are provided fixing in the shift register- 2 changes of the pulse sequence at the information input 13 of the device on their positive and negative fronts, regardless of the regular clock signal at the input 10. 2 Il. with S Y SO CX) --J to about ISO

Description

The invention relates to the field of automation and computer technology, can be used to troubleshoot digital circuits using signature analysis and is an improvement to the device according to the author. St. No. 1103201.

The purpose of the invention is to increase the reliability of the results of operation of the device.

FIG. 1 shows a diagram of the device; in fig. 2 - time diagrams of his work.

The device contains (Fig. 1) adder 1 modulo two, shift register 2, flip-flop 3, block 4, match 5, display 5, first shaper 6 short pulses, OR 7 j element, second shaper 8 short pulses, HE 9 and inputs: receive sync signals 10, start signals 11 and stop 12 and receive information 13.

The device works as follows.

Before the device starts operation, the register is reset to zero.

Adder 1, together with register 2, form the signature of the input sequence of pulse signals input to input 13. The logic state at input 13 is summed by adder 1 with the state of register 2 and is written offset to register 2 by a clock signal coming from the output of block 4, which leads to signature generation.

According to the Start signal arriving at input 11, the trigger 3 is set to the state allowing the passage of the shifting clock pulses from the output of the element OR 7 through block 4 to the input of register 2.

Sync pulse sequence

The keys providing the information shift in the register 2, formed at the output of the element. LIC 7, consists of three components: the first one is; regular a sequence of clock pulses and comes from the input 10 of the device (Fig. 2). Each of the sync pulses of the specified sequence is formed, for example, at the beginning of each of the same

time of controlled digital cycles in digital circuits according to auth.St. howling scheme. As a result of processing No. 1103201, different from the digital circuit of this clock at its output and at the input 13 of the device

the fact that, in order to increase the growth of the results of the device

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a sequence of pulse signals is formed, the duration and position of the pulse fronts in which are determined by the structure of the digital circuit and the sequence of information processing in it, i.e. this sequence is asynchronous.

The second component of the sync signal generated at the output of the element OR 7 includes short sync pulses generated at the output of the shaper 6 along the positive edges of the pulses at the input 13 (Fig. 2).

The third component of the sync signal generated at the output of the element OR 7 includes short sync pulses generated at the output of the shaper 8 along the negative edges of the pulses at the input 13 due to the polarity inversion of the element HE 9.

As a result of the joint action of the three components of the sync signal, the information in register 2 is shifted and the new code is written to the new next code both by the sync signal at input 10 and by the positive and negative edges of the pulses at input 13.

Due to this, a sequence of pulses at input 13 (Fig. 2), differing in the number of negative (and positive) fronts, is written to register 2 as different binary codes, and two different

5 according to the number of negative and positive fronts of a sequence of pulses at input 13 cannot be za. are written with the same code in register 2.

By the Stop signal, the actuation of the signal to the input 12 of the device, the trigger 3 is set to the state prohibiting the passage of the clock shifts from the output of the element OR 7 through

 block 4 to register 2. The shift in register 2 is terminated. The operator reads the resulting signature from the display 5 and, comparing it with the reference one, evaluates the validity of the digital circuit for subsequent troubleshooting.

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Claims (1)

Invention Formula Device for localization malfunction-. digital circuits on auth.St. No. 1103201, distinguished with the fact that, in order to increase the growth probability of the results of operation of the device, 312987204 The second device information shaper is entered into it, and the output through short pulses and the element is NOT; the input of the second driver is a short pulse that is connected to the input input of the owl - to the third input of the OR element. 011 1 10WOW1J 1 o o 2  Compiled by N., Belinkova Editor N. Egorov Tehred M. Khodanych Corrector M. Symborsk Order 888/50 Circulation 864 / Subscription VNIIG1I USSR State Committee for inventions and discoveries. 113035, Moscow, Zh-35, Raushsk nab. 4/5 , PproducedTvenno-polygraphic enterprise, Uzhgorod, Projecto st., 4