SU1231584A1 - Device for generating code sequences - Google Patents

Abstract

The invention relates to a pulse technique and a molset should be used in the processing of information in automatic data processing systems. The aim of the invention is to enhance the functionality and precision of the device. The device contains a pulse generator 1, a D-flip-flop 2, logic elements (LZ) And 3 and 14, frequency divider 4, delay element 5, counters 6, 8 and 15, comparison unit 7, memory devices 9 and 16, demultiplexer 10 , LE NOT II, shapers 12 and 18 short pulses, RS-trigger 13, register 17, LE OR 19 and 20, n channels 21 of the formation of codes, each of which contains a T-flip-flop 22, synchronized D-thrggg 23, In this way, the code generation channel can be executed either. element base. 1 e.p, f-ly, 1 ill. From usgg7rois / p and sonv cti 1 O 5S (L with lel eo M

Description

The invention relates to a pulse technique and can be used in the processing of information in automatic data processing systems.

The aim of the invention is to extend the functionality and the sweep of the device.

The drawing shows a block diagram of a device for formatting code sequences.

The device contains a pulse generator 1, D-flip-flop 2, first IZ element, frequency divider 4, delay element 5, counter 6, comparison unit 7, second counter 8, first memory device 9, de-multiplexer 10, HE element 11, first driver 12 short pulses, RS flip-flop 13, second element AND 14, third counter 15, second storage device 16, register 17, second short pulse shaper 18, first OR 19 element, second OR 20 element, n code generation channels 2, each of channels 21 contains a T-flip-flop 22, synchronized D-flip p 23, and the output of the generator 1 is connected to the first input of the first element And 3, the second input of which is connected to the output of the D-flip-flop 2, the output of the first element And 3 is connected to the first input of the second element And 14 and the input of frequency divider 4, the installation input of which is connected with the installation inputs of the first counter 6, the third counter 15 and the bus of the installation state, the output of the frequency divider 4 is connected to the input of the delay element 5, the output of which is connected to the even input of the first counter 6 and the first inputs of the n channels forming the information codes The e outputs of the first counter 6 are connected to the first inputs of the comparison unit 7, the second inputs of which are connected to the outputs of the first storage device 9, whose information inputs are connected to the data bus, the address inputs of the first storage device 9 are connected to the address bus and to the outputs of the second counter 8, counting the input of which is connected to the inverse output of the RS flip-flop 13, the direct output of which is connected to the second input of the second element I 14, the output of which is connected to the counting input of the third counter 15, whose outputs are connected us

address bus and address inputs of the second storage device 16, the information outputs of which are connected to the inputs of the register 17, the outputs

which is connected to the address inputs of the demultiplexer 10, the outputs of which are connected to the second inputs of the n channels forming the codes 21, the control input of the demultiplexer

10 is connected to the output of the comparison unit 7 and through series-connected elements HE 11 and the first driver of short pulses 12 with the S input of the RS flip-flop 13, the R input

which is connected to the output of the first element OR 19, the first input of which is connected to the input of the second counter 8, the first input of the second element OR 20, the third inputs

n channels forming codes 21 and bus Reset, the second input of the first element OR 19 is connected to the second input of the second element lUBi 20 and the output of the second shaper 18 pulse generator, the input of which is connected to the control output of the second storage device 16, the code of the second element OR 20 is connected to The P input of the register 17, the outputs of the n code-building channels, are the outputs of the device.

The device works as follows.

Considering that counter 6 is working

for addition, it is necessary to pre-record the codes of natural numbers of time (excluding the code of the number zero) in the memory device 9 from the code 000 ... 01 in the order of increasing binary numbers, and the corresponding code groups (if necessary, single codes) of the natural numbers of the numbers (number) channel can not be zero) channels (or channel numbers)

To the memory device 16, the codes in the group are placed in an arbitrary order and each last code of the group is marked with sign 1. The maximum possible number of codes in the group is equal to the maximum specified number of channels N. Before the device is started by the Reset signal, the counter is reset to zero. channel 17,

channels 21, RS flip-flop 13. At the same time, the Set to 1 signal sets all the triggers of counters 6 and 15 to one state. By window3

In order to set the counter 8 to the zero state, the decoder of the memory device 9 goes to the address 000 ... 00, and the time input code 000 ... 01 is read to the second input of the Slide 7 unit.

A trigger pulse, which enters the input of the D-trigger trigger 2 setup, sets it in a single state, allowing the pulses from generator 1 to pass through element 3 of input I of I4 and frequency divider 4 to input of delay element 5 from whose output delayed pulses simultaneously, they are fed to the input bus of the channel 21 and to the counting input of the counter 6.

The first pulse from the delay element 5 arriving at the counting input of the counter 6 transfers all its triggers to the zero state. The code of the state with m outputs 000, .. 00 of the counter 6 is fed to the first inputs of the synyon block 7. Comparison block 7 is triggered, the output of which is the result of the comparison as a logical O instead of a logical 1, since the block operates according to the principle of the time number code is preliminarily subtracted by the low-order bit, the result of the subtraction is compared with the status code of the counter 6 Logic O from the output of the comparison block 7 simultaneously arrives at the inverting information input of the demultiplexer 10 and through the HE element 11 to the driver 12 t output of which the generated short pulse arrives at the S input of the RS flip-flop 13, while it is set to one state. From the direct output of the RS flip-flop 13, a single potential allows the pulse 1 of the pulses from the output of element 3 to pass directly to the counting input the counter 15, the latter provides a sample of addresses of the codes of the channel numbers of the first group, on which the codes of the channel numbers are read from the memory 16 through the register 17, to the address input of the demultiplexer 10, providing Ku in ednichnoe state Trigg T s 22 channels 21.

Simultaneously with the arrival from the memory device 16

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it code channel number to the input of the register 17 feature code in the form 1 is fed to the input of the imaging unit 18, from the output of which is short and myc simultaneously enters through the OR element 19 to the R input of the RS flip-flop 13 and through the SHSh 20 element to the input Reset register 17. The RS flip-flop 13 is set to one, ensuring that the counter 15 stops and a new address code is generated at the outputs of the counter 8, respectively, providing a readout from the storage device 9 of the time number code 000 ... 02 to the second input of the comparison unit 7 until the second and pulses to the counting input of the counter 6. The second pulse arrives, simultaneously to the count-. The 8th input of the counter b, the outputs of which generate the state code 000. ..01, and the combination of 1a channels 21 (to the input of the D-flip-flop .23 sync) and the formation of code sequences in the channels 21, or in one channel, if in the memory device 16, instead of the first number code group

One code of the channel number is entered with a sign 1. The end of the formation of coding sequences in the channels (channel) 21 occurs, - if, after the next pulse arrives, the input of the counter 6 starts to receive a logical O on the inverse information input of the multiplexer 10, and groups of codes (code) of channel numbers 21, repeating (repeating) the previous group of codes (code) of channel numbers, arrive at its address input, and then a subsequent pulse goes to the corresponding channels 21, to the synchronization input of the D-flip-flop 23 .

The operation of the device is terminated after the logical 1 s t + 1 output of the counting 6 arrives at the synchronization input of the D-flip-flop 2 and it is reset to O.

Claims (1)

1. A device dp of forming code sequences containing a pulse generator, a first counter, the outputs of which are connected to the first inputs of the block compare 1, the first memory device and  the register, which is 51, in order to expand the functional possibilities and increase the accuracy of the transformation, a nerve and second elements AND, the element NOT, the first and second elements of the short impulses are additionally introduced , second zomnoobrazuyuschey device, the first and second elements OR, RS-thrngger, frequency divider, second and third counters, n channels of code formation, demultiplexer, D-flip-flop, the synchronization input of which is connected to the input bus. Start, input R is connected to the primary overflow output. the counter, the output of the D-flip-flop is connected to the first input of the first element And, the second input of which is connected to the output of the pulse generator, and the output of the first element And is connected to the first input of the second element And and to the input of the frequency divider, the output of which is connected to the input of the delay element , the output of which is connected to the counting input of the first counter and the first inputs n of the codes forming channels; the installation inputs of the first and pto counters of the frequency divider combining 1e and connected to the installation bus of the source STATE1; Avneni is connected to the control input of the demultiplexer and through successively connected elements NOT and its driver of short pulses to the S input of a KS flip-flop, the inverse iibrii output of which is connected to the counting-1W1M input of the second account chick. input1.1i of the first and second elements of the GSHI and with the second inputs of the n channels of the formation of codes and with the bus Reset, the second inputs of the first and second elements of the NW are interconnected and connected to the output of the second shaper of short pulses, the input of which Editor T, Parfenova Compiled by L, Klimov Tehred I. Bonkalo Order 2659/56 Tirgik 816Subscribe VNIIPN USSR State Committee but inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 1 industrial production, graphic design enterprise, Uzhgorod, ul. Project, 4 connected to the control output of the second storage device, the information outputs of which are connected to the information inputs of the register, the control input of which is connected to the output of the second OR element, the outputs of the register are connected to the address inputs of the demultiplexer) which are connected to the third inputs of the KODO135 generation channels of the information inputs the first and second memory devices are connected to the corresponding data buses, the address inputs of the memory devices are connected to the corresponding address buses The address inputs of the second storage device are connected to the outputs of the third counter, the output of the first UTI element is connected to the R input of the Trgger H8, the direct output of which is to the second input of the second element I, the output of which the third counter is connected to the counting input of the third counter; the outputs of the nerve counter are connected to the nerve inputs of the block, the second input of which is connected to the outputs of the impermeable memory device; Code codes are device outputs. 2, Device no. 1, 1, and 10, with the fact that each code generation channel contains T-flip-flops connected in series and a D-thringer, whose C input is the first input of the - mi codes, T-flip-flop T is the second input of the code generation channel, R-T-flip-flop input is the third input of the code generation channel, and the D-flip-flop output is the output of the code generation canap, Proofreader V. But ha