SU1305630A1 - System for dynamic synchronization and correction of object ranks in automatic control system - Google Patents

Abstract

The invention relates to automated control systems, in particular, to systems for assigning and dynamically adjusting the levers of objects, and can be used in implementing control transfer between objects of automated control systems of various priorities. The purpose of the invention is to increase the reliability and speed of the system. The goal is achieved by introducing into the system a group of elements OR, a group of inverters, a group of elements EXCLUSIVE OR, a switching device for slow and fast-varying parameters of ranking devices, a ranking device for a critical parameter, a ranking device for a combination of parameters and a memory block, which allows eliminate manual procedures for adjusting levers and Introduce automation of priority distribution. 6 hp f-ly. 11 il. (L with

Description

The invention relates to automated control systems. In particular, to systems for assigning and dynamically adjusting the ranks of objects of a complex ACS, and may be unused when implementing control transfer between objects of automated control systems of different ranks (priorities).

The need for such a system is due to the fact that when the various objects of the system go out of order (accident), which form one level of the Hierarchy and have a given status (rank), the reliability of control decreases, as the continuity of objects is disturbed when the control is taken on itself.

The purpose of the invention is to improve the reliability and speed of the system by introducing devices with the ability to assign ranks and eliminate manual procedures for adjusting ranks.

performed by a human operator. one

Figures 1 and 2 are a block diagram of the system; FIG. 3 is a diagram of a device for receiving and distributing parameters; 4 and 5 are diagrams of the main and auxiliary devices for ranking objects; 6 and 7 are schematic diagrams of a ranking device by a critical parameter; FIGS. 8 and 9 are schematic diagrams of the ranking device by set of parameters; figure 10 is a temporary diagram of the system; Fig. 11 shows the voltage patterns of a pulse sharpener at test points.

The system (Figures 1 and 2) includes the first group of registers 1, the first group of inverters 2, the first group of elements OR 3, the second group of elements OR 4, the first 5, the second 6, rub 7 and the fourth 8 groups of elements AND, the first element OR 9, second group 10, inverters, first register II, first pulse counter 12, first decoder 13, first 14 and second 15 triggers, first 16 and second 17 elements And, first 18, second 19 and third 20 delay elements, first inverter 21, first element OR-NOT 22, generator of 23 clock pulses, first frequency divider 24, indicator 25, perlo Memory 26, the third group of inverters 27, a first group 28 elements exclusive OR, 29.1 Switching device ranks the device

vanity by slow-moving 29.2 and fast-paced 29.3 parameter, ranking device 29.4 by critical parameter, ranking device 29.5 by set of parameters and the third group of elements OR 30. Switching device 29.1 (FIG. 3) contains a single time pulse sensor 31, input buffer register 32 The generator 33 clock pulses, the second frequency divider 34, the second 35, the third 36 and the fourth 37 groups of registers, the fifth 38, the sixth 39 and the seventh 40 groups of elements And, the second 41

and the third 42 pulse counters, the second 43 and the third 44 decoders, the second register 45, the fourth 46 and fifth 47-delay elements, the second inverter 48, the second element OR- 49, the third inverter 50 ,. the third element OR NOT 51, the second 52 and the third 53 OR elements and the third divider 54 frequencies.

The device 29.2 for ranking by a slow-moving parameter (Fig. 4) contains a parameter distribution block 55 comprising a second group of elements ORIGINAL OR 56, a fourth 57 and a fifth 58 pulse counters, a fourth decoder 59, a fifth decoder 60, the first encoder 61, the second block 62 memory, the third group of elements EXCLUSIVE OR 63, the fifth group of registers 64, the third trigger 65, the eighth 66, the ninth 67 and the fifth with the fifth 68 groups of elements And, the third 69, the fourth 70 and the fifth, 71 elements And, the fourth 72 and the fifth 73 elements OR or the fourth group 74 elements OR.

The device 29.3 for ranking by rapid parameter (Fig. 5) contains the parameter distribution block 55, the fourth frequency divider 75, the sixth counter 76, the sixth decoder 77, the eleventh 7B, and the twelfth 79 groups of elements I, the sixth element 80, and the fourth group 81 OR elements and five elements OR 82.

The device 29.4 ranking by critical parameter (Figures 6 and 7) contains the first group of adders 83, the fifth 84, the sixth 85 and the seventh 86 groups of registers, the fourth group of elements EXCLUSIVE OR 87, the seventh 88, the eighth 89, the ninth 90 and the tenth 9, second 92 and third 93 encoders, seventh 94, eighth 95 and ninth 96 decoders, tre3

97 and quarter 98 blocks of constant memory, five divider frequencies 99, sixth delay element 100, fourth 101, fifth 102 and sixth 103 groups of elements OR, sixth 104, seventh 105 and eighth 106 elements OR, seventh element AND 107 , the thirteenth group of elements AND 108, the fourth inverter 109, the fourth element S1I-NOT software, the fifth inverter 111, the fourth 112 and the fifth 113 groups of inverters, the fifth group 114 elements EXCLUSIVE OR and the fourteenth group 115 elements AND,

The device 29.5 ranking according to a set of parameters (Fig. 8 and 9) contains the sixth group 116 of the elements EXCLUSIVE OR, the adder 1.1 /, the seventh 118 and the eighth 119 groups of registers, the seventh 120 and the eighth 121 groups of elements EXCLUSIVE OR, the ninth 122 and the tenth 123 groups of registers, eleventh 124, twelfth 125, thirteenth 126, and four of 127 counters, tenth of 128 and eleventh 129 decoders, ninth group of 130 elements EXCLUSIVE OR, fourth trigger 131, seventh element 132 of delay, eighth element AND 133, fifteenth 134 and sixteenth 135 group e cops And, the ninth 136, tenth and eleventh .tsh 137 OR 138 elements, 139 elements of the seventh group OR, seventeenth and eighteenth 140 141 a group of AND gates and a sixth inverter 142.

In addition, the first 143 second 144 groups of system inputs, the input 145 of the device receiving and distributing the parameters of the first 146, the second 147 and the third 148 of the output groups of this device, the first 149 and the second 150 outputs of the device, the first 151, the second 152, the third 153 and the fourth 154 inputs, a group of 155 inputs, the fifth input 156, the first 157, the second 158, the third 159, the fourth 160, the fifth 161 and the sixth 162 outputs of the main device for ranking objects, the inputs 163, the group of inputs 164, the first 165, the second 166, the third 167, the fourth 168, the fifth 169, the sixth 170 and the seventh 171 inputs, the first 172, the second 173, tr 174 and fourth 175 outputs of the ranking device for quick-change parameter, the first 176, the second 177, the third 178, the fourth 179, the fifth 180, the sixth 181, the seventh 182 and.

304

the eighth 183 outputs, the group of inputs 184, the first 185, the second 186, the third 187, the fourth 188 and the fifth 189 outputs of the object ranking device by the critical parameter, the first 190, the second 191, the third 192, the fourth 93, the fifth 194, the sixth 195, seventh 196, eighth 197, ninth 198, tenth 199 inputs, first 200 and second 20 groups of outputs, first 202, second 203 and third 204 outputs of the object ranking system by the combination of parameters and system output 205. The system works in the following way.

The sensor 31 pulses of a single time generates information collection resolution pulses (IRSI), which are fed to the enable input of the input buffer register 32.

At each of the ACS objects, various parameters (for example, slow-moving, fast-changing, critical and.) Characterizing the performance and state of these control objects (OC) are formed and delivered to the communication channels. By entering system input 144 of the device for receiving and distributing parameters (Fig. 2), the OU parameters information is recorded in the input buffer register 32 under the condition that there is another pulse of information collection resolution,

After collecting the information in the input buffer register 32, the IDI, with its decay, starts the generator 33 of synchronized pulses. The sequence of clock pulses from the output of the generator 33 is fed to the input of the divider 34s, the output of which is formed by the sync pulses of the time channels (SIVK) that divide in time a set of characteristics of each op-amp. These pulses, having passed a delay element 46, the delay time of which is equal to the required pulse duration of the counter 41, the inverter 48 and the element OR NOT 49, represented the 1st pulse shaper, as well as the element OR 52, are fed to the fault input of the pulse counter 41.

In addition, pulses from the output of the generator 33 sync pulses arrive at the counting input of the input buffer register 32, sequentially issuing information from the output of the latter, and as sync pulses of code pulses

positions (SIKP), which determine the location in the time channel of information, go to the pulse frequency divider 54. The pulses from the output of divider 54 follow with the frequency of changing information types (for example, the code of the OU number, each of its parameters, etc.) and are fed to the incremental input of the pulse counter 41, increasing the state of the latter by one each time. From the counter 41, the binary code goes to the decoder 43, which sequentially connects to the information channel first the shift register 45, the information of the OS number and the synchronization input - the SPTN - and the elements of the corresponding groups 38 - 40 - to the inputs selection of temporary storage registers of current parameter codes 35-37.

The decoder 44 decrypts the contents of register 45, which is the code number of the next OU, and connects to the information bus only a group of registers 35 - 37 that are reserved for the current record; their parameters of this control object

 A pulse of 58 pulses with a parallel code is fed to the input B of the elements EXCLUSIVE OR 56 of the block of the distribution of parameters (Fig. 4). The inputs 155 of the group A of the elements 56 are connected (the number of this OS has been transmitted at the current time to the outputs 146 of the corresponding pe40

channel). In addition, the outputs of the decoder 44 are connected to the element OR 53, the pulses from the output of which are fed to the incremental input of the counter 42 pulses. The latter calculates the number of operational OU participating in the current cycle of collecting and transmitting information. Synchronized inputs of the registers 35 - 37 receive the sync pulses of the code positions.

After all the information from the input buffer register 32 has been processed in the pulse counter 41, the decoder 43 and 44, and the register 45, a high potential is generated at the zero output of the decoder 44, which by means of the delay element 47, the inverter 50 and the IPI element -NE 51 (temporary epures, fig. II) is converted into a short pulse. This pulse, passed through the element OR 52, is fed to the fault input of the pulse counter 41 and is outputted to the output 150 of the receive-and-distribute device 29.1 parameters, and also resets the generator 33 and the input buffer register 32.

The pulse from the output 150 of the device 29.1 as a start pulse is fed to a single trigger input

temporary storage 37 of the first parameter codes of all OA. When the code formed by the counter 58 and the code recorded in one of the 35 registers of the second group 35 coincides, the output of the corresponding EXCLUSIVE OR 56 elements is generated 1, which simultaneously enters one of the inputs of the OR element 72 and one of the inputs of the address code encoder 61 . From the output of the element OR 72 1 enters the incremental input of the counter., 57 pulses, themes. by increasing its state by 1.

A parallel code from the output of the pulse counter 57 goes to the information inputs of the decoder 59 and to the inputs A of the EXCLUSIVE OR elements 63. The decoder 59 sequentially pushes the information inputs of the registers 64 of the fifth group. These inputs receive the codes of the OS numbers, which are permanently stored in block 62 of the permanent memory. The addresses of the cells of the fixed memory unit 62 in which the codes of the OS numbers are formed by the encoder 61. Moreover, the code of the OS numbers that characterizes 50 is recorded in the first register 64 of the fifth group of registers.

55

65, setting it to one state and opening element I 69. The next pulse from the output 205 of the generator is 23 clock pulses of the system

enters through the element AND 69 to the incremental input of the pulse counter 58, which performs two functions; generates reference information for comparing the values of parameters of all operable opamps and is a control element when polling and assigning the sequence number to the registers 64 by the first parameter. The outputs of the counter 58 pairs. Are connected to one

the inputs of the elements And 66, 78 and 115

device groups 29.3 and 29.4, to the other inputs of which unit potentials are supplied from the corresponding elements of the EXCLUSIVE OR 63 and 114 groups.

Consider the operation of the ranking device 29.2 for the mediated foaming parameter.

From the outputs of the elements And 66 of the eighth group, the information generated by the pulse counter 58 by a parallel code is fed to the input B of the elements EXCLUSIVE OR 56 of the block of the distribution of parameters (Fig. 4). Inputs 155 group A of elements 56 podklyu0

five

temporary storage 37 of the first parameter codes of all OA. When the code generated by the counter 58 and the code recorded in one of the 5 registers of the second group 35 coincides, the output of the corresponding EXCLUSIVE OR 56 elements is generated 1, which simultaneously enters one of the inputs of the OR element 72 and one of the inputs of the address code encoder 61 . From the output of the element OR 72 1 enters the incremental input of the counter., 57 pulses, themes. by increasing its state by 1.

A parallel code from the output of the pulse counter 57 goes to the information inputs of the decoder 59 and to the inputs A of the EXCLUSIVE OR elements 63. The decoder 59 sequentially pushes the information inputs of the registers 64 of the fifth group. These inputs receive the codes of the OS numbers, which are permanently stored in block 62 of the permanent memory. The addresses of the cells of the fixed memory unit 62 in which the codes of the OS numbers are formed by the encoder 61. Moreover, the code of the OS numbers that characterizes 0 is recorded in the first register 64 of the fifth group of registers.

five

7I

with the smallest first parameter, and in the last - the code number of the OS with the largest parameter. In addition, the current code from the output of the counter 57 goes to the inputs A of the EXCLUSIVE OR element 63, where it is compared with the number code that comes from the pulse counter 42 (counts the number of operable op-amps) to the input of the auxiliary device 29.3 for ranking objects. At the output of the EXCLUSIVE OR 63 elements, when the codes coincide, a zero pulse is generated, which is fed to the second inputs of the E 66th group elements, thereby terminating the access of information from the pulse counter 58 to the inputs of the EXCLUSIVE SHSh 56 elements

groups. I

The quick parameter ranking device works in a similar way.

Information from the fourth group of registers 37 for temporary storage of parameter codes that have critical values (parameters and their critical values) is fed to the inputs 173 of adders 83 of the first group of adders, and the inputs B of the adders 83 receive the values of about, and the input A oixp passed the corresponding a group of inverters 112 that convert the direct code of critical parameters to the inverse. The input P1 of the adders 83 of the first group of adders is constantly fed 1, they implement the operation & B. oi. .

in the case when Lo; O, at the output P2 of the adders 83 of the first group of adders, a zero potential is formed, which is inverted by the inverters 113 and connects the registers 85 of the sixth group of registers. In the case when U oi O, a high potential is formed at the output of P2, connecting registers 84 of the fifth group. Thus, after processing the information stored in registers 37 of the fourth group of the group, in cyt aTopax 83 of the first group, parameters that exceed their critical value will be recorded in registers 86 of the seventh group, and the parameters Y, whose values are less than their critical values, 84 registers of that group of registers will be recorded.

05630 8

Further processing of the parametron is carried out according to procedures similar to those described for device 29.2. The special feature consists of 5 only in that the first half of the registers 86 of the seventh group of registers contains the ranking of the OS for d and OS O, and the second half for iicc - 0.

After codes of numbers of the OS

 O are arranged in devices 29.3 and 29.4 (each in its parameter), the elements EXCLUSIVE OR of the third 63 and fifth of the 114 groups give zero potentials, which cover the elements AND 66, 78 and 115 of the corresponding groups of elements AND on the one input and after inverting by inverter 115 open the corresponding elements And 70, 81 and 107 and the group of elements And 68.

0 In addition, these potentials, having passed the elements of And 70 and 71 and OR 73, reset the counter 58 to the initial state.

The decoder 60 using the group of elements And 68 polls the registers 64, the counter 76 and the decoder 77 using the group of elements And 80 interrogates with the corresponding 1x registers of the parameter distribution block, the counter 90 and the decoder 96 using the groups of elements ШШ 101 and И 108 made poll registers 86 groups.

Pulse frequency dividers 75 and 99 allow polling the registers of the parameter distribution unit with a frequency of i times (i is the number of OA) less than a similar poll of registers 65 and i times more than a similar poll of registers 86 of the seventh group of registers. Such a ratio of clock frequency following clock allows to obtain all combinations of codes at the outputs of registers 64 and fifth.

 groups and registers 86 of the seventh group of registers, which through the corresponding fourth group of elements OR 74, the fifth group of elements OR 102, arrive at inputs 195 and 196 of the device 29.4 (Figs. 8 and 9), i.e. elements EXCLUSIVE w. 116 groups. Simultaneously from the counter 58 through the elements And 66 groups, the counter 76 and the counter 90 through the corresponding

 inputs 192 - 194 information is provided

on the adder P 7.

I

With the coincidence of codes in elements 116 (this happens with the combination of pe913

The gistras in which the code of the number of the same OA is recorded) at their output is formed 1, opening one input elements of the AND 140 group, the other inputs of which are connected to the corresponding outputs 185 of the decoder 96, which sequentially connects each of the registers 118 and 119 groups to adder 117, at the output of which, by this time, the sum of the serial numbers of registers 64 and 86 and the corresponding registers of the auxiliary device for ranking objects is formed, the code number of the same OA is recorded in KOT013YX.

The amount code is recorded in one of the registers 118 (or 119) of the group, the position of which corresponds to the position of one of the registers 86 of the group in which the code of the OS number is recorded. This allows you to establish a one-to-one correspondence between the object number and the sum of the ranks of this object by separate parameters . After the last group register 119 is loaded, the trigger 131 is set to one. A single potential from the output of the flip-flop 131 opens the I 133 element one at a time, the other input of which is connected to the generator-23 clock pulses. The next clock pulse generator 23, the pass element And 133, is fed to the incremental input of the counter 127, which forms the current value of the code received at the inputs B of the EXCLUSIVE W1I elements 120 and 121, the inputs of which receive the contents of the corresponding registers 118 and 119 of the group, which is sums of OU ranks by parameters.

When the codes at inputs A and B of elements 120 and 121 coincide, single impulses are formed at their outputs, which through the elements OR 137 and 136 are supplied to the incremental inputs of the corresponding counters 125 and 124. These counters, together with the decoders 129 and 128, perform the final ranking of the OS numbers the outcome of the sums of their ranks separately. parameters and connection of group registers 122 to enter in them codes of OS numbers, which have LoS O, and registers 123 groups to register in them codes of OS numbers, in which ftct-i О

30 10

The information inputs of registers 122 and 123 receive information from the outputs of the corresponding elements 134 and 35, the inputs of which receive information from the OR 102 and 103 groups, if there is a resolving potential at the direct output of the trigger 131. Generator pulses arrive at the synchronizing registers 122 and 123 23 clocks from output 205,

Simultaneously, the signals from the outputs of the elements OR 136 and 137 through the element OR 138 are sent to the incremental input of the counter 126, the current code from the output of which goes to the input A of the group of elements EXCLUSIVE OR 130, to the input B of these elements the code of the number of operable DI from output 149 counter 42 block 29.1. When the information at the inputs of elements 130 is equal, a pulse is generated, which, after a delay by the delay element 132, records the last code in registers 122 and 123 as a zeroing pulse: to input 145 of counter 42, to input 154 of trigger 65, to the fault input of counter 57, to input 166 of block 55, to the second input of the element OR 82, the pulse from the output of which goes to the fault input of the counter 76, to the input 176 of the device 29.3, to the fault inputs of the counters 126 and 127, as well as to the zero input of the trigger 131, high potential of the zero output which through obos the shrushs triple represented by the delay element 100, the inverter 109 and the OR element NOT, zeroed the counter 90. Thus, in group registers 122 and 123, the object number codes are ranked by all parameters.

I

In addition to information about the parameters

each OU reports information about its control readiness (for example, Object XXX is ready (not ready) to be controlled), which in the form O (Not ready) or 1 (Ready) goes to the control object and is stored in register 11 "

The pulse frequency divider 24, the input of which is connected to the generator output of the 23 clock pulses, outputs pulses, the follow-up period of which is calculated taking into account the entire timing diagram of the system.

n1

by the time of the arrival of the next im- pulse from the divider 24, the register 11 is filled with new information on the readiness of the control unit to be controlled, and each register register 11 is rigidly assigned to its object. The next impulse of the divider 24, passing the elements OR 3 and 30, connects each of the registers 1 and opens a group of elements AND 5 through one input, to the other inputs of which information is fed from the corresponding outputs 200 and 201 of registers 122 and 123. This information through the elements OR 4 groups are listed in registers 1.

At the same time, the impulse from the divider 24, delayed by the delay element 18, arrives at the single input of the trigger 14, the latter is transferred to the single state and thus starts the OU rank adjustment cycle,

A single potential from the output of the trigger 14 opens the element AND 16 in one input. The next clock pulse generator 23 through the second input element And 16 is fed to the incremental input of the counter 12. This counter, counting the pulses of the generator 23, forms the current code arriving at the inputs of the decoder 13 and, as the current cell address, to the input of the memory block 26 These are the codes of the OS numbers in the order of their increase. The decoder 13 performs a sequential polling of the states of the bits of the register 11. If O is fixed in some of the bits of register 11, then the output of the inverter 10 corresponding to this bit 10 will have 1 and the corresponding AND 8

will be opened one by one.

With the arrival at the second input of the element AND 8 of the pulse from the decoder 13, this pulse through the element OR 9 goes to one input of the elements AND 7. At the same time, the OU number codes read from block 26 successively in time arrive at the input A of the elements EXCLUSIVE OR 28, on each of which receives its own code of the OU number from outputs 200 and 201 of registers 122 and 123. If the codes coincide in some element 28, the output of the latter forms a hinge impulse, which after inerting the corresponding inversion of group 27 arrives at the second turn etstvuyuschego AND gate 7.

63012

When the pulses coincide in time at the output of the element OR 9 and at the output of the inverter 27 of the group, at the output of the corresponding element And 7 a pulse is formed which, as a zero signal, arrives at the corresponding register 1, has wrapped its contents.

After resetting all registers 1,

In which codes of OS numbers that were not ready for control were stored, trigger 15 is transferred to the one state by the impulse of the 1st bus of the decoder 13, and trigger 14 by this impulse returns to the initial state. The high potential of the single output of the trigger 15 opens the element AND 17 for passing the clock pulses of the generator 23 to the synchronous inputs of the registers 1. The inverters 2 groups, in the corresponding registers 1 which have erased the codes of the op-amp numbers, generate pulses that through the element: OR 3 connect the corresponding registers for write information from subsequent registers.

With the arrival of the clock pulses of the generator 23, the synchronous inputs of the registers i shift information from

subsequent registers in previous After the information is shifted (rank adjustment), it is displayed on the indicator 25 (Fig. 14) by a pulse from the output of the delay element 20, the delay time of which is equal to the maximum information correction time, trigger 15 returns to the initial state. The unit potential from the zero output of this trigger

The pulse intensifier, represented by delay element 19, the inverter 21 and 1 SHI-HE element 22, has wrapped the contents of counter 12. The system is ready to receive new correction information.

Claims (6)

1. The system of dynamic synchronization and adjustment of the ranks of objects in the ACS, containing the first register, clock generator, the first pulse frequency divider, three delay elements, two triggers, two PJ elements, the first OR-NOT element, the first ISH-1 element, the first counter of the pulses, the first decoder, the first inverter, two groups of inverters, four groups of And elements, two groups the OR elements, the indicator, the first group of registers connected by permitting inputs to the first outputs of the OR elements of the first group, and informational to the outputs of the OR elements of the second group, and the outputs are connected to the corresponding indicator inputs, the inverter inputs of the first group are connected to the outputs of the corresponding registers of the first group , the outputs of the elements AND of the first group are connected to the first inputs of the elements OR of the second group, connected by the second inputs to the outputs of the elements AND the second group whose inputs are connected to the outputs according to vstuyuschie registers of the first group connected by the fault inputs to the outputs of the elements AND the third group, connected by the first inputs to the outputs of the first element OR whose inputs are connected to the outputs of the elements AND the fourth group connected by the first inputs to the corresponding outputs of the first decoder, the second inputs - with outputs, inverters of the second group, connected by inputs To the outputs of the first register, connected by information inputs with the first group of system inputs, and the synchronizing input - with the output of the generator a clock output connected to the input of the first frequency divider and fflylcov, soedinen-- Nogo exit to the first inputs of AND gates of the first group with a second g The input of the OR elements of the first group and the input of the first delay element, the output of which is connected to the S-input of the first trigger, the R-input of which is connected to the output of the last digit of the first decoder, and the output of the first trigger connected to the first input of the first And element input with the output of the clock pulse generator, and output with the counting input of the first counter connected by the output to the inputs of the first decoder, the output of the last bit of which is connected to the S input of the second trigger connected to the direct output ohm to the first input of the second element And, and the inverse output to the input of the first inverter and to the input of the second delay element, the output of which is connected to the corresponding inputs of the first element OR NOT connected to the output of the first pulse counter, the stroke of the third delay element is connected to the input of the second trigger, and the input is connected to the output of the second element AND connected by a second input to the output of the clock generator, characterized in that, in order to increase reliability and speed, a third group of elements OR) are introduced, the third group of inverters, the first group of elements EXCLUSIVE OR, switching device, ranking devices by slow- and fast-changing parameters, ranking device by critical parameter, ranking device by cumulative parameters and the first memory block connected by inputs to the outputs of the first pulse counter, and outputs to the first inputs of the EXCLUSIVE OR elements of the first group connected by outputs to the inputs of inverters of the third group whose outputs are connected to the second inputs of the elements AND of the third group, the first inputs of the elements OR of the third group are connected to the output of the second element, And, and the second inputs are connected to the output of the first pulse frequency divider, and the outputs are connected to the clock inputs of the registers of the first circuit, the device inputs switching is connected to the second group of system inputs, the first output is connected to the first input of the ranking device by a set of parameters, the second input of which is connected to the output of the clock generator, the second output of the switching device is connected to the first input of the ranking device by a second input to the output clock generator, the first, second and third groups of the outputs of the switching device. are connected to the corresponding input groups of the device Ani from the critical parameter of the ranging device bystromen yuschemus parameter and ranging device according medlennomen yuschemus parameter, and the switching device input to a first output podklEochen jointly ranging device parameters connected to the first input of the ranking device by a critical parameter, the second and third outputs of the ranking device are slowly connected to the first input of the device 151305630 ranking by fast-paced parameter and c. the second input of the ranking device by the critical parameter, the third input of which is connected to the output of the clock generator, the second input of the ranking device by the quick-release parameter is connected to the first output of the ranking device by the combination of parameters, the first and second groups of outputs 10 of which are connected to the inputs of the corresponding elements Both the first group and the second inputs of the EXCLUSIVE OR elements of the first group, the first output of the ranking device according to a slowly changing parameter is connected to Reverse the input of the ranking device by a set of parameters, the fourth input of which is connected to the first output of the ranking device by a fast-changing parameter, the second output of which is connected to the fifth input of the ranking device by a combination of parameters, the sixth input of which is connected to the fifth output of the ranking device slowly - a variable parameter connected by the sixth output to the fifth inputs of the ranking device by a critical parameter, the sixth input of which is connected to the third output of the device the rankings for the fast parameter, the third input of which is connected d the first output of the device 20 25 sixteen 2. The system according to claim 1, characterized in that the switching device contains an input buffer register, a clock pulse generator, second and third pulse frequency dividers, second, third and fourth vert groups of registers, fifth, flat and seventh the groups of elements AND, the second and third counters, the second and third decoders, the second register, the fourth and fifth delay elements, the second and third elements lOTi-HE, the second and third elements OR, and the sensor of pulses of a single time connected by the output to the trigger input of the clock generator and to the enable input of the input buffer register, the group of inputs of which is the group of inputs of the device and which is counted; the input is connected to the output of the clock pulse generator and the input of the second pulse frequency divider connected to the inputs of the fourth delay element and the second inverter whose outputs are connected respectively to the first and second inputs of the second OR element NOT connected to the first input of the second OR element whose output is connected to the reset input of the second pulse counter connected by a counting ijx to the output of the third pulse frequency connected by the input to the output of the synchronizing grease generator by the totality of parameters, 35 pulses, and the outputs of the second counter of the seventh, eighth and ninth co-pulse inputs through the second decipher connected to the first inputs of the corresponding elements And the fifth, sixth and Secondly, they are connected respectively to the second, third and fourth outputs of the ranking device by a critical parameter, the five outputs of which are connected to the third input of the ranking device by a slowing parameter, the fifth input of which is connected to the fourth output of the ranking device by the sixth parameter the input is with the first output of the switching device and with the seventh input of the ranking device for the fast-changing groups and the permit input 40 of the second register connected in house sync generator to output clock pulses, an information input of the second register input connected to the output 45 buferno- th register and the outputs of the second register through the third decoder are connected to second inputs of AND gates of the fifth, sixth, and seventh groups and to the inputs the third element OR, and the zero voltage, the input of which is connected, connects the third decoder to the output of the clock generator inputs of the fifth delay element and pulses and the seventh input of the third inverter connected to the output by critical parameter - by moves to the first and second respective inputs of the third element OR- 55 NOT, the output of which is the second output of the device and is connected to the second input of the second element 1 SHI and the reset inputs of the clock generator and the input borax, wherein the first output, and fourth and eighth inputs coupled respectively to a tenth input, with the second and third outputs ranging device of the set of parameters. 10 15 0 0 five sixteen 2. The system according to claim 1, characterized in that the switching device contains an input buffer register, a clock generator, second and third pulse frequency dividers, a second, third and fourth branch of a group of registers, five, three and three the seventh group of elements is AND, the second and third counters, the second and third decoders, the second register, the fourth and fifth delay elements, the second and third lOTi-HE elements, the second and third OR elements, and a common time pulse sensor connected to the output of the generator start sync pulses and to the enable input of the input buffer register, the group of inputs of which is the group of inputs of the device and which is counted; the input is connected to the output of the clock pulse generator and the input of the second pulse frequency divider connected to the inputs of the fourth delay element and the second inverter whose outputs are connected respectively to the first and second inputs of the second OR element NOT connected to the first input of the second OR element whose output is connected to the reset input of the second pulse counter connected by a counting ijx to the output of the third pulse frequency connected by the input The seventh group and the enabling input 40 of the second register, connected by the synchronization input to the output of the clock generator, the information input of the second register is connected to the output of the input buffer register 45, and the outputs of the second register through the third decoder are connected to the second inputs of the elements And the sixth and seventh groups and to the entrances The triple register, the setup input of the third pulse counter is connected to the input of the switching device, the counting input is connected to the output of the third OR element, the outputs are connected to the first output of the switching device. information inputs of registers of the second, third and fourth groups are connected to the output of the input buffer register, synchronous inputs are connected to the output of the synchronizing pulse generator, allowing the inputs of registers of the second group are connected to the outputs of elements And of the fifth group, allowing the inputs of registers of the third group f5 of the And element and the first the entrance of that Dy - with the outputs of elements And the sixth group, allowing the inputs of registers of the Fourth group - with the outputs of elements And the seventh group, and the outputs of the registers of the second, third and fourth groups are connected respectively to the first, second and N-th groups of outputs of the switching device. I 25 thirty 3. The system according to claim 1, characterized in that the device ranked 1 has the third trigger, the eighth, ninth and tenth groups of elements AND, the third, fourth and fifth elements AND, the fourth rpjmny elements OR, a five pulse counter, a fifth decoder, and a parameter distribution unit, connected by the first and second inputs, respectively, to the input group and the fourth input of the ranking device by slow-speed parameter, the second input of the parameter distribution unit, the third input, the Q block of the parameter distribution sub-. It is connected to the outputs of elements And of the eighth group, the first output of the parameter distribution unit is connected to the first input of the fourth element I, the second output is connected to the reset input of the fifth pulse counter, and the output group of the parameter distribution unit is connected to the first inputs of elements And the ninth group, connected by outputs to the inputs of the fourth group SHS elements, the outputs of which are connected to the first output of the device, ranking by the slower parameter, the S input of the third trigger signal is connected to the first input of the ranking device van for slow-slowing parameter, R-input of the third trigger to its fourth input, and high element And, the second input of which is connected to the third input of the ranking device for slower-lowering parameter, and the output connected to the fourth block input, the first input of the right element And it is connected to the fifth input of the ranking device with a slow-slowing parameter, and at the fourth input of the fourth element I - to the first output of the block connected by the second output to the reset input of that counter, the inputs of the fifth decoder are connected Mento And tenth group and outputs subkey us to respective second inputs of AND gates of the nine groups, with n outputs of the counter are connected to second and third outputs ustroyst va, and the output of the third AND element, in 35 moves of the elements of the tenth group and the output of the fourth element of AND are connected respectively to the fourth, nth and sixth outputs of the van rank device by the slow-losing parameter. 45 4. The system of claim 1, so that the wound device for fast-paced parameters contains a parameter distribution block, the fourth divider of the clock, the sixth pulse counter, a sixth decoder, the twelfth group of elements, and , the fifth group of elements AND JQ is the sixth element of AND, the fifth element of the IL is the eleventh group of elements of AND, connected with the first inputs to the first input of the ranking device by the baseing parameter, the first  the input of the distribution unit is parameter-connected to the second input of the ranking devices by the quick-rate parameter and to the first input of the fifth OR element connected by the output to the course of the third trigger is connected to the first input of the third element I, the second input of which is connected to the second input of the ranking device by the slowing parameter, and the output to the counting input of the fifth pulse counter connected to the first input of the elements of the eighth group and the first inputs of the elements And the tenth group, the second inputs of which are connected to the third input of the ranking device according to the slowing parameter, the third inputs are connected to the output of the fourth five 0 Q And, the second input of which is connected to the third input of the ranking device by a slow-moving parameter, and the output is connected to the fourth input of the block, the first input of the fourth And element is connected to the fifth input of the ranking device by a slow-slowing parameter, and the second input of the fourth element I to the first output of the block connected by the second output to the reset input of the fifth counter, the inputs of the fifth decoder are connected to the outputs of the elements of the tenth group, and the outputs are connected to the corresponding second inputs of the elec And the ninth group, the outputs of the fifth, the counter are connected to the second and third outputs of the device, and the output of the third element And, vy5 moves the elements of the tenth group and the output of the fourth element And are connected respectively to the fourth, fifth and sixth outputs of the ranking device by slowing parameter. 4. The system of claim 1, wherein the ranking device for the fast-changing parameter contains a parameter distribution unit, a fourth frequency divider, a sixth pulse counter, a sixth decoder, a twelfth group of elements AND, n the second group of elements OR, the sixth element AND, the fifth element OR, the eleventh group of elements AND, connected by the first inputs to the first input of the ranking device for fast-paced parameter, the first the input of the parameter distribution unit is connected to the second input of the ranking device in terms of the fast-paced parameter and the first input of the fifth OR element connected to the output of the user The setting input of the sixth pulse counter, the counting input of which is connected to the output of the sixth element I, connected by the first and second inputs to the fourth and fifth inputs of the device, respectively, and the third input to the output of the fourth pulse frequency divider, the input of which is the third input of the device, output the sixth counter through the sixth decoder is connected to the corresponding first inputs of elements And the twelfth group, connected by a second input to a group of outputs of the parameter distribution unit, outputs of elements And d The eleventh group is connected to the inputs of the elements OR of the fifth group, the outputs of which are connected to the first output of the device, the inputs of the parameter distribution unit are connected to the group of inputs of the device, the second input is connected to the sixth input of the device, and the third input of the block is to the outputs of the elements And the eleventh group, the second the inputs of which are connected to the first output of the parameter distribution unit connected by the second output to the fourth output of the ranking device by a fast-changing parameter, the second output of which is connected to the input the sixth decoder connected by the last bit to the second input of the fifth OR element, the output of the fourth frequency divider is connected to the third output of the device. 5. A system according to claims 1, 3 and 4, characterized in that the parameter distribution unit contains the fourth and fifth elements OR, the fifth group of registers, the fourth pulse counter, a quarter decoder, the first encoder, the second memory block, the second and the third group of elements EXCLUSIVE OR, the first inputs of the elements EXCLUSIVE OR of the second group are connected to the group of inputs of the block, the second input of the block is connected to the synchronous inputs of registers of the fifth group connected by outputs to the group of outputs of the block connected with acc favoring the fourth decoder output, the inputs of which are connected to the inputs of elements per- Vym exclusive OR of the third group, the second inputs of which are connected to the fifth input unit, and an output connected to the first exit 0563020 the block house, information inputs of the registers of the fifth group are connected to the output of the second memory block, the input of which is connected to the output of the first encoder connected to the inputs of the EXCLUSIVE OR elements of the second group and the inputs of the fourth OR element connected to the counting input of the fourth counter to pulses connected to the output the input of the fourth decoder, the last bit of which is connected to the first input of the fifth OR element, connected by the second input to the first 15 to the input of the block, the third input to the fourth input of the block, and the output to the second output of the block, the third input of the parameter distribution block is connected to the second inputs of the elements of the IS0 KEY OR the second group. I 6. Pop-1 system, characterized in that the ranking device by critical parameter 5 contains the sixth delay element, the sixth, seventh and eighth groups of the OR elements, the sixth, seventh and eighth elements of the OR, the seventh element of the AND, the thirteenth and fourteenth groups JQ elements AND, the fourth and fifth inverters, the fourth element OR-NOT, the annular group of inverters, the fourth and fifth groups of elements EXCLUSIVE OR, the first group of adders, the fifth, sixth and seventh groups of registers, the seventh, eighth, ninth and the tenth counters, the seventh, eighth and ninth decoders, the second and third encoders, the second and third memory blocks, Q is the fourth group of inverters, whose inputs are the inputs of a device input group, and the outputs are connected to the first inputs of the adders of the first group connected by the second inputs 5 with inputs of the device input group, and outputs with the inputs of the corresponding inverters of the fifth group, and to the enabling inputs of the registers of the fifth group, connected informational inputs to the second inputs of the adders of the first group, allowing the inputs of the registers of the sixth group The information inputs are to the second outputs of the adders of the first group, the first inputs of the EXCLUSIVE OR elements of the fourth group are connected to the outputs of the fifth and sixth registers rpynti, the second inputs are connected to the outputs. 35 21 the elements of the fourteenth group and the output are connected to the cooTBeTCTByrotHHM. inputs of the second and third encoders as well as the sixth and seventh elements OR, connected to the counting inputs of the seventh and eighth pulse counters and to the inputs of the eighth element OR connected to the counting input of the tenth pulse counter connected by the output to the first inputs of the EXCLUSIVE OR elements of the same group, the solenoent outputs with the input of the fifth inverter connected by the output to the first inputs of the elements of the fourteenth group and to the fifth output of the device, and the input to the first input of the seventh element I, the second and third inputs of which are connected to the fifth and sixth inputs of the device, respectively, and the output is connected to the input of the fifth frequency divider connected by output to the counting input of the ninth counter connected by a reset input to the output the fourth element OR NOT, the inputs of which are connected to the outputs of the sixth delay element and the fourth inverter, input: which are connected to the fourth input of the device, the inputs of the seventh and eighth decoders are connected to the inputs of the seventh and eighth pulse counters, and the outputs are connected to the enable inputs of the registers of the seventh group, connected by information inputs to the outputs of the third and fourth memory blocks connected to the inputs of the second and third encoders, respectively, and the outputs of the registers of the seventh group are connected to the first inputs of the thirteenth group of elements connected the second inputs to the outputs of the elements OR the sixth group, connect the outputs of the ninth decoder connected to the output of the ninth pulse counter, the inputs of the elements of the seventh and eighth groups are connected to the outputs of the elements of the thirteenth group, the second inputs of the elements of the fourteenth group are connected to the second output of the device, synchronizing the inputs of registers The fifth, sixth and seventh groups are connected to the third input of the device, the second inputs of the EXCLUSIVE OR elements of the fifth group and the OR elements of the sixth group are the seventh and eighth inputs of the device Twa accordingly, you,, fO f5 30,563,022 the moves of the elements of the OR of the seventh, eighth groups, the outputs of the ninth counter are connected to the second, third and fourth outputs of the device, respectively. 7, Pop. 1, characterized in that the ranking device for the totality of parameters comprises the seventh, eighth and ninth groups of the elements OR, the eighth, ninth, tenth and eleventh groups of registers, the eleventh, twelfth, thirteenth and fourteenth counters ,, tenth and eleventh decoders, the fourth counter, the seventh delay element, the eighth element - AND, the fifteenth, sixteenth, seventeenth and eighteenth groups of elements AND, the ninth, tenth and eleventh elements OR, the seventh group of elements OR, the sixth inverter, adder, connected to the information inputs registers of the eighth and ninth groups, the outputs of the elements of the I and the fifth and sixteenth groups are connected to the information inputs of the registers of the tenth and eleventh groups connected by the outputs from the first and second groups of outputs, respectively, the first in the moves of the EXCLUSIVE OR elements of the sixth group are connected to the outputs of the elements of the OR of the ninth group, and the output is connected to the first inputs of the elements of the seventeenth and eighteenth groups connected by outputs to the inputs of the registers of the seventh and eighth groups, the direct output of the fourth trigger is connected to the first inputs - I will give the elements of the fifteenth and sixteenth groups and to the first input of the eighth element AND, the outputs of the ninth and tenth elements OR are connected respectively to the counting inputs of the eleventh and twelfth counters and to the inputs the eleventh element OR connected by the output to the counting input of the thirteenth counter, the outputs of the elements EXCLUSIVE OR the seventh and the eighth groups are connected to the inputs of the ninth and tenth elements OR, respectively, the first inputs of which are connected to the outputs of the registers of the eighth and ninth groups, and the second inputs connected to the output of the fourteenth counter, connected by a counting input to the output of the eighth element And, the inputs of the tenth and eleventh decoders are connected to the outputs of one 2313 the twelfth counters respectively, and the outputs of the tenth and one, the decryptors are connected to the enable inputs of the registers of the tenth and eleventh groups, the first inputs of the EXCLUSIVE OR elements of the ninth group are connected to the output of the thirteenth counter, and the output is connected to the sixth inverter the first output to the input of the seventh element-fO my and ninth inputs of the device, the delay, the output of which is connected to the fault inputs of the eleventh, twelfth, thirteenth, fourteenth counters, the R-input of the fourth the second inputs of the elements of the seventeen eighteenth groups and the S input of the fourth trigger are connected to the tenth input of the ranking device by 0 24 the devices, the inputs of the adder are connected to the third, fourth and fifth inputs of the device, the second and third inputs of the elements EXCEPT the SHOCK OR of the sixth group are connected to the sixth and seventh inputs of the device, the second inputs of the elements of the Fifteenth and Sixteenth groups, as well as the inputs of the elements OR nine or nine the groups are connected to the eighth and ninth inputs of the device, the second inputs of the elements of the seventeenth, eighteenth groups and the S input of the fourth trigger are connected to the tenth input of the ranking device by co-trigger and to the first output of the device, 15 of the parameters, the outputs of the eleven, the second inputs of the elements EXCLUDE ALREADY OR of the ninth group are connected to the first to the input of the device, synchronizing the inputs of the registers of the eighth, ninth groups and the second input of the eighth 20 elements And are connected EXCLUSIVE OR of the seventh and in my groups are connected to the second outputs of the device, the inverse output of the fourth to the trigger by the second input Ztaunt. tftp.klyuchen to the device. third exit parameter sets, outputs EXCLUSIVE OR of the seventh and eighth groups are connected to the second outputs of the device, the inverse output of the fourth trigger of the parameter’s parameters, the outputs Key to device. third exit  , - at 1 I II Vt UCH TJ, V  s ,, 1II 1 The same five ss to c / iea 1  I Osh 2t-7. J / .LJ FIG. 2 sJI "--E I" tj  raVii fv. five fe “i f 0 S: glb | § | se 9 4 t CHO f g CO S "S" 5 "WH I “W .. J n M ten s se s S - 185 ,,. .ShZ (SVM1.2L) t gbl Fy (cet, ". w3) t. t / Swm Logg -; 5i Uas / v87 / room 138 Well TQif.pa. Fig.d. the end