SU1591072A1

SU1591072A1 - Shift register

Info

Publication number: SU1591072A1
Application number: SU884608114A
Authority: SU
Inventors: Nikolaj A Kvitka; Vladimir P Kozhemyako; Alim I Koronovskij; Leonid S Levakov
Original assignee: Vinnitsky Politekhn Inst
Priority date: 1988-11-23
Filing date: 1988-11-23
Publication date: 1990-09-07

Description

The invention relates to computing, automation and digital measurement technology and can be used in sequential arithmetic logic devices for converting a serial code into a parallel code with a base - ^ 2 ¹ and vice versa when developing distributors of both single and pair pulses, as well as at

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creating ADC bitwise coding. The purpose of the invention is the extension of the functionality consisting in ensuring the shift of codes with the base - {ζ. The goal is achieved by introducing the elements And 3-6 and in each digit of the register, starting with the second junior multiplexer 2. Such a set of features allows you to shift information both binary and codes with a base on one

and two digits to the right. At the same time, the register is capable of converting parallel binary codes and codes with a base into serial codes and vice versa of successive codes into parallel codes. In this case, due to the simultaneous attempting of the first and second inputs of the shift register, respectively, of even and odd bits of the sequential code, the conversion in it occurs twice as fast as in the known one. 1 il.

1 15 CL— 9 ^Tg - ъ - 3 four Λ g '4ι ίϊί ⁷ g ΐ eight Chi ^- th eleven 9l

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The invention relates to computed. technology, automation and digital. can be used in arithmetic logic logic weighing devices of sequential action to convert a serial code into a parallel code with a base 4? and vice versa in the development of distributions of both single and pair pulses, as well as _{in the} creation of bitwise coding ADCs.

The purpose of the invention is the extension of the functionality contained in. providing shift codes with a base - ^ 7.

The drawing shows the functional scheme of the shift register. 2θ

- Shift register contains три-triggers 1 ₀ -1 _η _ ·,, multiplexers 2, -2 _п ~ ₍ , first 3, second '4, third 5 and fourth 6 elements AND, information outputs 7 ₀ “7η”, parallel code , input 8 + 25

control multiplexers, the first synchronization input 9, the first 10, and the second 10 ^ information inputs. of a sequential code, the second 11 and the third 12 inputs of the register synchronization, the first 13 and second 14 information outputs of the sequential code and the shift bus 15.

The register works as follows.

Converting a serial binary code or code a {7 into a parallel code requires the supply of a serial code to input 10, starting with the upper digits, feeding signals to the shear bus and simultaneously with the clock signals to input 9. You must first attach a logical signal to input 8 of the register. In this case, the conversion will be carried out on a consistent basis by a bitwise recording of the shift to the right by one bit of information in the register. The transformation of the serial code into parallel ends at the moment of writing the information about the low-order bit to the trigger

1 ₀ . To accelerate the conversion of a sequential code into a parallel one, it is necessary to input a signal of a logical “1” to input 8, and to input 10 and 10 ^ to attach information of even and odd bits of a binary code or code 77, respectively. Due to the simultaneous arrival of

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row information on inputs 10. and 10 x '

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sync signals to input 9 and shift pulses in the shift bus 15, information will be recorded in triggers 1 ₀ -1 and shifted to the right by two; discharge at the same time. Therefore, the conversion process in this case will be twice as fast in comparison with the previous case.

Converting a parallel code into a serial code on the shift register will require synchronous signaling to the bus 15 of the register and signals to the input 11 of the register. Then, successively in time at the output of the 13th register, information will appear on each digit of the code previously recorded in the register, starting with the higher digits. 8 bus 8 register with a logical signal “0”. If at the input 9 of the register signal logical "1", the conversion will be carried out in>. Two times faster, as the shift to the right occurs simultaneously by two bits. The serial code thus appears sequentially in time at the outputs 13 and 14, for which impulse signals must synchronously go to the register bus 15 and to the inputs 11 and 12,

• For a sequential shift of one digit to the right of the unit recorded in the trigger 1 _o , the presence of a logical signal “0” in the register bus 8 and pulse signals in the shift bus 15 is necessary. Sequential shift to the right by two digits of information recorded in triggers 1 ' _s and 1 ₍ requires the input of a single signal register and pulse signals on the bus 15 of the register. Input results in this case will be present sequentially in time, starting with output 7 ₀ (7,) output (Ί) ·

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In comparison with the known, the proposed shift register performs a shift of two digits to the right in one clock cycle, which is necessary for processing the information presented in the code with the base T ?. Simultaneously, the register converts sequential code into parallel and vice versa. Due to the simultaneous conversion of even and odd digits of the source code.

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Claims

Claim

The shift register containing in each ΐth digit (ί = 1, η, where η is the row size of the register) три-trigger, and the direct output of the trigger of the ηth category and direct outputs of the trigger (1, n-1 ) bits, respectively, are the first information output of the sequential code and information outputs of the parallel register code, the C inputs of the flip-flops are connected to the register shift bus, characterized in that, in order to expand the 15 base - \ {2 ^ c. it contains four elements And and in each ί-digit, where ί = (1, η-1), a multiplexer, the output of which is connected to the ϋ-input of the trigger (ϊ + 1) -γο register bits, direct output of the trigger ( ί + 1) -th digit is connected respectively to the first and second information inputs of multiplex -5 sors (ί + 1) - and (ι + 2) -γο bits of the register, direct trigger output (p + 1-> digit is connected to the first information input of the multiplexer of the n-th digit of the register, the control inputs of the multiplexers are combined and are the input of the control of the register multiplexers mode, Ora information input multiplexer; (ί + 1)

(where ί = 1) the second digit of the register is connected to the output of the first element And, the second input of which is combined with the second input of the second element And is the first synchronization input of the register, the first inputs of the first and second elements And are respectively the first and second information inputs of the serial register code , the output of the second element I is connected to the ϋ-in ^ at the first register trigger, the direct outputs of the η-th and (n-1) -bits of the register are connected to the first inputs of the third and fourth elements, respectively, the second inputs of which These are the second and third synchronization inputs of the register, respectively, and their outputs are the second and third information outputs of the sequential register code, respectively.