SU1262533A1 - Function generator - Google Patents

Abstract

The invention relates to the field of automation and computer technology. The function generator contains a block for setting the parameters of functions, two buffer registers of ordinates, and a digital-analog function approximation block. loop register, trigger, multiplexer, analog-to-digital converter and code comparison block. An increase in the reliability of the formation of output signals is achieved by comparing the specified and actual values of the ordinates of the reproduced functions at the boundaries of the subintervals of the approximation. The comparison operation is performed both by dp of one-time and for replicable function sections using a code comparison block, one input of which is supplied with analog-to-digital conversion output codes, and another input is output code of one of the buffer perHcd -, ( Y d dv, commutated using a multiplexer and a trigger. 1 s, n, f-ly, 3 ill.

Description

The invention relates to automation and computer technology and can be used, in particular, in the generation of analog control signals in electrohydraulic control topics for mechanical loading during repeated static tests of various structures. The purpose of the invention is to increase the reliability of the formation of output signals. Figure 1 presents the block diagram of the functional generator; FIG. 2 is a diagram of a digital-analog function approximation unit; FIG. 3 is a block diagram for setting parameters of functions. The function generator (f. 1) contains the block 1 setting the function parameters, the first 2 and second 3 buffer registers of the ordinates, the digital-analogue block 4 of approximating functions, the register 5 of the cycle, the trigger 6, the multiplexer 7, the analog-digital converter 8 and the block 9 of the code comparison. The digital-analog unit 4 approximations of functions, the input of the functional generator (Fig. 2), contains two working registers 10 and 1 1 ordinates, a controlled pulse generator 12, a reversible counter 13, an AND 4 element, an OR 15 element, a memory block 6 , switch 17, trigger 18, and three digital-to-analog conversion bodies 19. The function parameter setting unit 1 can be executed on a microprocessor or on an address counter 22, a memory node 23, a half-cycle register 24, a code comparison node 25 and a half-cycle counter 26 (FIG. 3). The function generator operates as follows. At the preparatory stage, the initial position from the memorizing node 23 to register 2 is assigned the ordinate code of the end point of the first section of the approximation, to register 3, the ordinate code of the initial first section, and the 24 half-cycle register — the number of half-cycles (if the section is not cyclic, then the number of half cycles equals one). Registers 10 and P, counter 13 and trigger i 8 of block 4 are cleared. Thus, in the initial state at the outputs of the converters 19 - 21 there are zero potentials which arrive at the output of the function generator. It should be noted that the length of the bit grid of the storage unit 23 can be chosen such that the information in registers 2,3 and 24 is recorded simultaneously. On the Start command (the setting chain and starting the device are not shown in the drawing) the information from register 2 is rewritten into the first working register 10. As a result, the potential of the first section's final ordinate is formed at the output of the converter 20. Since the counter 13 is zero, the zero code of the first cell is generated at the output of the memory block 16 and the output of the converter 19, and hence the signal output of the device, receives only the potential of the initial ordinate from the output of converter 21 (in particular, zero). This signal is fed to the input of the analog-digital pre-use 8 and, on command, the Start is converted into digital form and fed to the input of the comparison unit 9. The multiplexer 7 is set to start position through trigger 6 in such a way that the second input of comparison unit 9 is connected to the output of register 3, on which the initial ordinate code of the first segment is written. If the codes on the two inputs of comparison unit 9 are equal, then an impulse appears that triggers block 1 and establishes the trigger 18 of block 4 into one state. The output signal of the trigger 18 removes the lock from the reversible counter 13 (gives permission for the passage of pulses to the counting input of the counter 13 from the generator 32). Thus, the formation of the first section of the approximation of the output signal of the device begins. If at the moment the pulse arrives at the end of the conversion from the converter 8, the codes at the inputs of the comparison unit 9 are not equal to each other, then the function generator does not start and it is necessary to eliminate the cause that caused the inequality of the named codes. Such code comparison is carried out further after the processing of each section of the function is completed. The pulse signal from the output of block 9 comes to the counting input of the counter 26 of block I and records in it a unit indicating the end of one section. If the section is not cyclic, then the comparison node 25, comparing the state of the counter 26 with the unit state of the register 24, outputs at the first output a signal to the counting input of the address counter 22 and resets the counter 26. The code at the output of the counter 22 changes from the next cell node 23 Registers 2, 3 and 11 receive new information on the next section. If the section is cyclically repeated, then the comparison node 25 at the second output issues a signal. The loop enters the register 5 and. prohibiting by means of the element AND 14 of block 4 the rewriting of information from the buffer register 2 into the working registers 10 and II. The information in the working registers does not change, which leads to the generation of a cyclic signal until the half-cycle counter 26 accumulates a number equal to the specified number of half-cycles in register 24. In this case, the comparison unit 25 compares the signal from the first output to the address counter 22 and register 5. The Cycle command is removed and the Nova information is fed to the digital output of block 1. In the process of generating a cyclic signal, the codes of registers 2 and 3, which characterize the maximum and minimum functions, remain unchanged. The signal from the pulse output of the terminal end of the block 4 at the extreme points of the generated cyclic function blocks the operation of the counter 13 via the trigger 18, starts the converter 8 and through the switching trigger 6 and the multiplexer 7 alternately connects one of the inputs of the block 9 to the outputs of the register 2 or 3. The other input of block 9 at this moment receives information about the corresponding current extremum from the output of the converter 8. The result of the comparison from the output of block 9, similarly described, switches block 1 and black Trigger 18 removes blocking of counter 13. Upon completion of testing the cyclical part of the output signal, all dependences on the number of extremes (even or odd), trigger 6 is set to the position through which the multiplexer 7 connects the comparison unit 9 to the output register 3. This excludes a violation

synchronization when monitoring the output signal of the function generator,

Thus, the considered functional generator, by eliminating the errors of the output signal, allows to increase the reliability of its formation.

Claims (2)

1. A function generator containing a function setting block, connected by a digital output to the input of the first buffer register of ordinates, and Cycle and Lack of Cycle outputs to the control inputs of a cycle register connected by an output to the data enable input of the digital-analog function approximation block connected to information the input to the output of the first buffer register of ordinates, and the signal output to the output of the function generator, characterized in that, in order to increase the reliability output signals, a multiplexer, a trigger, an analog-to-digital converter, a code comparison unit and a second buffer register connected to the digital output of the function parameter setting block, made in the form of a memory block, and the output to the first information input are added to it the multiplexer connected by the second information input to the output of the first buffer register of ordinates, and the control input to the direct output of the trigger, the inverse output of which is connected to the information input of the trigger a, connected by a setup input to the output of the cycle register, and a write enable input to the pulse output of the subinterval of the digital-analog function approximation unit and the start input of the analog-digital converter, the multiplexer output connected to one of the code comparison unit inputs, the other input of which is connected to the digital the output of an analog-to-digital converter connected by an analog input to the signal output of the digital-analogue approximation unit 1: and functions, and the output of a signal with the gating input of the code comparison unit, the output of which is connected to the address input of the function setting unit and the resolution enable input of the digital-analogue function approximation unit. 2. The generator according to claim 1, which is based on the fact that the digital-analog function approximation block contains two operating registers, a controlled pulse generator, a reversible counter, AND and OR elements, a memory block, a switch, a trigger and three digital-analog converters, the digital inputs of the first and second working registers of the ordinates are connected to the information input of the digital-analog function approximation unit, the write enable inputs of these registers are connected to the corresponding switch outputs, the input of which is connected N to the output of the And element connected by the first input to the data transmission enable input of the digital-analog approximation function block, and the second input to the pulse output of the subinterval of the digital-analog function approximation block, the trigger reset input and the output of the OR element, whose inputs are connected to the overflow signs and resetting the reversible counter connected by a digital output to the address input of the memory unit, and the counting input to the output of a controlled pulse generator, while the digital output of the block the memory is connected to the digital input of the first digital-analog converter, the output of which is the signal output of the digital-analog function approximation unit, and the analog input is connected to the outputs of the second and third digital-analog converters connected by digital inputs to the outputs of the first and second working registers of the ordinates, respectively, and the lock input the reverse counter is connected to the trigger output, the setup input of which is podklk (chen to the resolution enable input of the digital-analogue block of the approximate AI functions.