SU1254526A2 - Device for training operators of control systems - Google Patents

Abstract

The invention relates to automation and computing, is intended for the training and training of operators, and is an improvement to the device according to the author. St. No. 744713. The device contains a teacher 1 console, an operator console 2, a program task block 6, ring shift registers 10, an evaluation block 11, a decoder 12, AND elements 13, an OR element 14, a delay element 15. Introduction to the device of an additional element SHSh 16, an element OR-NOT 18, additional elements AND 17 and 21, a block of 22 elements AND, additional elements 20 and 24 of a delay, block 23 of a reversible counter 19 allows to expand its didactic possibilities by introducing the operator self-monitoring and prompt error correction. 1 il. § (ABOUT

Description

 one

The invention relates to automation and computer technology, in particular to technical training aids, is intended to train and train operators in the troubleshooting skills of electronic equipment, and is an improvement to the invention by the author. No. 744713.

The purpose of the invention is to expand the didactic capabilities of the device.

The drawing shows a block diagram of the proposed device.

The device for training control system operators contains a teacher 1 console, a onepal-opa console 2 consisting of interchangeable modules 3, each of which has a first fault coding output 4 and a second output 5 of an operator response signal, block 6 of a program task, of the same name bits 7–9 of the circular shift registers 10, evaluation unit 11, decoder 12, group of elements AND 13, element OR 14, delay element 15, additional element OR 16, additional element AND 17, element OR-NOT 18, reversible counter 19 ( fixation of results performing optimum insulating algo-. rhythm), an additional delay element 20, the additional AND gate 21, the AND unit 22, display unit 23 and an additional delay element 24.

. In the process of performing the task, the controller on the remote control 2 detects the functional symptoms of the malfunction introduced by the teacher, determines the set of modules to be replaced, and the optimal sequence of their replacement.

At the end of the troubleshooting, the evaluation unit 11 receives signals of the number of delayed modules replaced by the operator from the output of the first delay element 15, signals of the sequence of replacement of the modules from the outputs of the group of elements And 13 and the code of the optimum number of modules replaced from the first group of outputs of the program setting block 6 The signals are analyzed in evaluation unit 11 according to established criteria, and the corresponding evaluation is issued to console 1 teacher.

The first delay element 15 is designed to provide reliable switching elements 12, 13, 16

545262

and 18. Reversible counter 19 serves to fix the process of replacing the alleged faulty modules with respect to its optimal algorithm. The second delay element 20 provides an enable signal to the display unit 23. The delay time of the signal element is chosen longer than the delay time of the signal

10 produced by an additional element 24 delay. The additional delay element 24 is designed to reliably overwrite new information in counter 19.

 five . The device works as follows.

Before starting work, the teacher introduces a faulty module into the console of 2 operators. Then on signal

20 from the teacher 1 console from the output 4 of the faulty module, a fault coding signal is output to the corresponding input of the program task block 6. When the specified

The 25 inputs of the program setting unit 6 generates parallel codes of signs (for example, numbers) of modules, which are covered by the functional indication of a faulty module and must be

30. Replaced by the operator in the process of troubleshooting. These codes, through some groups of outputs of block 6, arrive at the information inputs of the same-named bits 7–9 of the ring.

35 shift registers 10. The number of operations of the optimal algorithm before the operator starts working is displayed on the information board 23. The circuit for recording information of the channel number of operands (5 of the optimal troubleshooting algorithm is not shown in the diagram. Each set of like bits of registers 10 forms a register that stores the code of one module, and

placement of module codes in bits

7-9 corresponds to the optimal sequence of their replacement. When troubleshooting. In this case, in the last bits 9, the module code is placed, which should be replaced with the first one, and in the first bits 7 - the module code, which should be replaced with the last one. From the outputs of the last bits of the 9th module code, replaced by the first one, goes to the decoder 12. At the same time, the corresponding output of the corresponding element I 13 is generated at the corresponding output of the decoder 12. At the same time, block 6 of the first

group of outputs in the evaluation unit and the installation inputs of the counter code number corresponding to the optimal number of modules to be replaced when determining the fault module. With the replacement of the first of the modules 3, a corresponding signal is formed at the output 5 of the response actions of the console 2 of the operator. This signal is fed to the second input of the corresponding element And 13.

If the operator correctly identified the module replacement sequence and the first module replaced by it corresponds to the module replaced by the first in the optimal troubleshooting, the inputs of the And 13 elements match the signals from the output of the decoder 12 and from the input 5 of the operator’s console 2. At the same time, the specified AND element opens and issues a match signal to the evaluation unit 11, as well as to the corresponding inputs of the OR 16 element and the OR OR NOT 18 element. Next, the signal from the output of the OR 16 element is fed to the first input of the AND 17 element. At the same time, the signal from output 5 operator 2 through the element OR 14 and the delay element 15 is fed to the third input of the evaluation unit 11 and to the second input of the element 17. After the triggering, the latter sends a signal to the shift inputs of the registers 10 from the output, a program shift is made in K jpbDC. In this case, the codes of the modules recorded in the same bits of the register

The lines 10 are shifted to the subsequent bits, for example, from bits 7 to bits 8, etc., and from the last bits 9 to the first bits 7, which ensures the preservation of the fault finding program. After the first shift corresponding to the first replacement, the module code that should be replaced by the second is in bits 9. This code is also decrypted in the decoder 12 and prepares the corresponding element AND 13 for opening. From the output of the delay element 15, the signal also goes to the counting input of the counter 19, the first input of the element 21, the input of the delay element 20 and the reset input of the block 23. The binary code from the output of the counter 19 enters the inputs of the block 22. This code corresponds to the number of operations of the remaining optimal algorithm. The signal delayed by the time of resetting the previous information in block 24, from the output of the delay element 20 is fed to the inputs of block 22 and enable

s tO

15 20 5 o

five.

0

five

0

shafts light the next information. Highlighting a number smaller than one for the number of operations of the optimal algorithm allows the operator to perform the following operation.

If the replaced module does not correspond to the module replaced by the first one, the signals on the corresponding AND 13 element do not coincide, and the evaluation unit 11 does not receive a matching signal. At the same time, the signal from the output 5 of the operator console 2 through the element -OR 14 and the delay element 15 is fed to the third input of the evaluation unit 11, in which the number of modules replaced by the operator is counted. In the absence of signals of coincidence at the outputs of elements AND 13, an element OR-NOT 18 is triggered, and from its output a signal is fed to the input of element AND 21, when a signal appears at its other input, it is triggered and the output signal goes to the delay element. The signal delayed by element 24 for the time required to record the new information on the subtracting input of counter 19 is fed to the summing input of counter 19 and sets it to the state preceding the incorrectly executed operation. The signal from the output of the delay element 20, delayed by the time of resetting the previous information in block 23 and reliable rewriting of new information on the summing input of the counter 19, is fed to the input of block 22 and allows the information to be illuminated. In this case, it does not change. The operator is given the opportunity to correct the mistakes made in the execution of the optimal algorithm. When the operator replaces the next module, the described process is repeated.

Claims (1)

Invention Formula Device for training control system operators according to auth. No. 744713, characterized in that, in order to expand the didactic capabilities of the device, the additional OR element and the first AND element, the OR OR NO element, the second additional AND element, the first additional delay element and the reversible counter, the second input are introduced into it. which is connected 5 125A526, To the program setting block, the sequential delay element and the third input, the second complementary counter counter wisely is connected to the delay element, the delay element, the other element and the display unit, the second terminal of the AND element, the second input first trails reversible counter inputs an additional element AND, a second optional element OR, and an elevator input of the second additional element OR are NOT connected to the outputs that And, the input of the second additional elements I.