SU1320831A1 - Device for teaching operators - Google Patents

Abstract

This invention relates to the field of ergonomics and can be applied as an integral part of a simulator. The purpose of the invention is to expand the didactic capabilities of the device. This goal is achieved by the fact that the blocking unit 6, the code generator 8 and the response result memory block 10 are entered into the known device containing the operator panel 2, the standard memory unit 5, the response result generation unit 4 and the registration unit 11. The signal from the imaging unit 8 generates the signals of the branches and the vertices of the operator’s graph of the operator, and each branch of the operator’s graph of the operator corresponds to one of the ways to solve the learning task, and the graph’s vertex is the unit control action of the operator being trained. The signals from the output of block 5 are fed to the inputs of block 4 and through the decoder 3 - on board 1, where they are presented to the operator. The operator’s reaction signals from the console 2 output are fed to the corresponding inputs of block 4, in which they are compared with standards. If the operator has performed the action timely and correctly, then on the indicator of block 11 the branch and the top of the graph are highlighted. Otherwise, according to the signals from block 4, the shaper 8 will stop working, the localization node 7, the error will fix the location of the error, and then the block 11 will highlight the location and the nature of the error. Block 10 blocks the branches of the graph when the operator performs the actions. After the correct control action is performed, the operator may experience a state of uncertainty in the correctness of the perfect action. In doing so, he may perform a repeated right or wrong action. In this case, the node 6 according to the signal from the remote control 2 will fix it and generate a signal in block 11 to highlight the error. 1 h. the item of f-ly, 9 ill. i sl so y oo o so

Description

The invention relates to ergonomics, in particular to operator training devices, and can be used as an integral part of a simulator.

The purpose of the invention is to expand the didactic capabilities of the device.

FIG. 1 shows the general structure of the device; in fig. 2 is a block diagram of the formation of response results; in fig. 3 - diagram of the operator's console; in fig. 4 is a diagram of a standard memory block; in fig. 5 - blocking device diagram; in fig. b - the scheme of the localization of errors; in fig. 7 is a diagram of the driver codes; in fig. 8 is a diagram of the response result memory block; in fig. 9 is a diagram of the board and the control unit.

The device for training operators contains an information board 1, an operator console 2, a decoder 3, a response result generation unit 4, a pattern memory block 5, a blocking node 6, an error location node 7, a code generator 8, a control block 9, a result memory block 10 answers and block 11 registration.

Block 4 contains (Fig. 2) comparison node 12, element 13 OR, delay elements 14-16, element 17 AND, element 18 2И-OR, elements 19-22 AND-NOT, triggers 23-26, counter 27, start buttons 28 and reset 29.

The console 2 contains (Fig. 3) the authorities 30 discrete control actions of the operator and the register 31.

Block 5 is a reprogrammable ROM 32.

Node 6 contains the triggers 33 and 34 (Fig. 5).

Node 7 contains a register 35 and a decoder 36 (Fig. 6). Shaper 8 contains 4FIG. 7) generators 37 and 38 and counters 39 and 40. Unit 10 is made on the basis of RAM 41 (FIG. 8). The remote control 1 and node 9 contain keys 42 and indicators 43.

A device for training operators operates as follows.

In order to improve and control the characteristics of the operator’s work under deterministic conditions, as well as in accordance with the requirements of the instruction, a corresponding operator’s program was introduced in block 5.

The deterministic operator program is formalized by means of graph theory. The number of branches of the operator's graph corresponds to the number of ways to solve a particular professional task. The number of vertices on the branch of the graph corresponds to the number of operator control actions in each method of solving the problem.

Each vertex and branch of the reference graph of the operator is assigned a binary code, which is generated by counters 39 and 40.

These code signals from the outputs of the imaging unit 8 are sent to the address buses of block 5, and this specifically determines the information area of the memory, which stores the correct solutions for each method of resolving any limiting problem situation (task)

the corresponding graph or standard, and on the data bar of block 5, binary codes are generated corresponding to the correct solution of the given situation (task). Binary signals of the vertices and branches of the reference graph are generated by shaper 8 (Fig. 7) containing a generator 37 for the vertices of the graph and a generator 37 for the branches of the graph, and the period of the clock pulses of the generator 37 is selected 10 times shorter than the minimum length of time required to perform an arbitrary controlling action by the operator in the process of solving a problem situation or task in one way or another. The period of the clock pulses of the generator 38 3-4 times less than

0 period generator clock 37.

Code signals from the output of the counter 40

also go to one of the inputs of the block

10 for prohibition of comparison and to the input of block 4.

Output codes from data block 5 bus

5 is fed to the input of block 4 and node 7, as well as to the decoder 3, where they are logically transformed and fed to board 1 for presentation to the operator by means of visualization and signaling. The operator, perceived in the stimulus information displayed on board 1, acts on the organs 30 of the console 2. Each organ 30 of the console 2 corresponds to a certain binary code used in drawing up a program of deterministic operator activity (operator graph). When the operator acts on any body 30, two signals are generated: the binary code of the control body and the tracking signal, which are fed to register 31. Next, the code signals from the output of register 31 are fed to the input of block 4, and the wake-up signal is sent to one of the inputs node 6

for localization of re-decision.

Consider the operation of block 4 (Fig. 2).

By briefly pressing the button 29

trigger 26, register 35 of node 7 (FIG. 5),

The binary counters 39 and 40 of the driver 8 (Fig. 7) are set to the zero state, while the output signal of the trigger 26 prohibits the operation of the generators 37 and 38, and also enters the node 9, where via the control key 42 it lights up the "Stop.

0 When the button 28 is pressed, the triggers 24 and 25 are set to the zero state, and the triggers 23 and 26 are set to one, while the output signal of the trigger 26 enables the generators 37 and 38, and also suppresses the “Stop and lights the“ Work in node 9. The unit level at the output of the element 21 sets the block 10 to the mode of recording a single signal coming from the output of the element 20.

there is a single level, and consequently, at the output of element 18, a single level that causes the entry in block 10 zero and the exception hereafter

the release mode of the recorded information and the operating cycle of the entire device starts.

The output code of the counter 40 causes the graph, then at the output of the element 15 there is

recording of a single level at all addresses a zero level signal blocking the form block 10, permitting by this to compare the un-shaping by element 18 of a single signal

mation signals unit 4 for all levels. If the coincidence does not occur in the graph of the operator's activity. Once, i.e., the operator did not execute the control signal at the output of the element 22 of the assisting action, then at the output of the element 15

triggers triggers 33 and 34 to zero state. When the button 28 is depressed on the falling edge of the signal at the output of element 22, the register 31 is set to the zero state, and a zero signal from the comparison of this branch of the graph, the stroke of the element 21, the block 10 is translated to If there is a single signal on

element 17 when codes and a single blocking signal of a branch generated by block 5 coincide; element 19 is set when the control action fails — 5 trigger 23 to the zero state, operator at the input of element 13, an output signal at trigger output 23

there is a zero code, and at the output the element causes the formation of a single

that 13 is a zero signal that blocks the signal at the output of element 22, which

signal output elements 17 and 18. enters the register 31. On the falling edge

If for the required time interval of the overflow pulse arriving from the operator performed a controlling action, 20 counter 40, trigger 23 is set, i.e., at the input of element 13 there is an arbitrary single state, the output is different from zero code, then on its signal element 20 sets the output register 31 - a single signal. Binary zero state. Counter capacity 40

counters 39 and 40 generate an address-equal to n, where n is the number of branches of the graph

signals of branches and vertices of graph 25 (methods for solving the problem), for block 5. Binary codes of block 5 Binary counter 27 is intended for

arrive at one inputs of node 12. for other fixing of incorrect actions of the operator,

The inputs of which receive binary codes and also for stopping the operation of the device from the remote control 2. If the codes coincide at the exit when the operator has finished

Node 12 has a single signal. In accordance with the solution of the problem. The capacitance of the match with the single signals at the input of the ZO of the chip 27 is equal, where n is the number of the element 17 produces a single signal of the graph (ways to solve the problem).

If there are 10 single signals at the output of the block, the counter 27 is set to the zero state. The filling of the counter 27 occurs on the signals of the generator 38.

operator in the process of solving the problem. 35 wrong control action. At the same time, for the remaining branches of the graph, the operator or if the control did not complete - in which the codes did not coincide, the action at the output of block 10 is

received with the output of the console 2 and block 5, the zero signal for all branches of the graph

at the output of node 12, there is a signal of zero (decision methods) of the activity graph of the opal level, which prohibits the development of the rectifier. In this case, for / g + 1 clock cycles of the unit signal by element 17 and the resolver 38, the counter 27 generates a unit signal generation of the elemental overflow pulse, which sets trigger 26 to the zero state.

The output signal of the trigger 26 prohibits the operation of the generators 37 and 38 and, do

The information is written from block 5 to register 35. After conversion in decider 36, information is fed to the outputs of node 9 to indicate the correct data 18. A single signal at the output of element 18 causes the output element 21 of the unit level to form

(record), and at the output of element 20 - well, to the input of node 9, extinguishes the scoreboard "Work and

left level, which leads to writing to block 10 zero at the address of one or another branch of the graph and prohibiting further comparison of the information signals of these branches of the operator's activity graph.

lights the “Stop,” indicating that the operator has erroneously acted during the task. At the same time, the previous correct operator action, indicated on the board of node 9, indicates the location of the error made by the operator at the subsequent stage of the task.

In the last clock of the generator 38, before changing the vertices of any branch of the graph, the operator’s output bus of the block 5 generates a single signal arriving at elements 18 and 19 for

lights the “Stop,” indicating that the operator has erroneously acted during the task. At the same time, the previous correct operator action, indicated on the board of node 9, indicates the location of the error made by the operator at the subsequent stage of the task.

If the control action of the operator is imperfect, there is a zero signal at the output of the element 13, which

blocking a given branch of the graph and resetting 55 through element 16 by a register overflow signal 31. at the output of counter 27, sets a trigger. In this case, if node 12 determines herr 24 to be in one state. The output coincidence of codes for the vertex of this veto signal of the trigger 24 is outputted at the output of a unit level, and therefore, at the output of element 18, the unit level, which causes the entry in block 10 zero and the exception further

from the comparison of this branch of the graph, If there is a single signal on

to the input of node 9, extinguishes the board “Work and

lights the “Stop,” indicating that the operator has erroneously acted during the task. At the same time, the previous correct operator action, indicated on the board of node 9, indicates the location of the error made by the operator at the subsequent stage of the task.

9 and through the control key 42 lights up the scoreboard “Imperfect action, which specifies the nature of the error made by the operator at the subsequent stage of control.

If the operator controls the wrong action, there is a single signal at the output of the element 13, which, by an overflow signal at the output of the counter 27, sets the trigger 25 to the single state. The output signal of the trigger 25 is fed to the input of the node 9 and, via the control key 42, lights up the “Incorrect action” board, which specifies the nature of the error made by the operator at the subsequent stage of control.

After the correct control action is performed, the operator may have uncertainty about the correctness of the performed action, and it is possible to re-act on the organs 30 of the console 2. When the organs 30 are exposed to the triggers 33 and 34 of the node 6, a tracking signal is issued. At the first tracking signal, the trigger 33 is set to one. With the second and subsequent tracking signals, a single output signal of the trigger 33 sets the trigger 34 to one state. The output signal of the trigger 34 is fed to the input of the node 9 and, via the control key 42, lights the “Repeated decision” panel, which specifies the nature of the error made by the operator. The initial installation of the flip-flops 33 and 34 is performed by the output signal of the element 22, the formation process of which is described above. At the initial installation of the node b, the “Re-solution of node 9” panel is quenched.

After the operator completes the task, the register 31 of the console 2 is in the zero state, and block 5 generates a branch blocking signal, which causes an operator in the event of no response to the operator, setting the trigger 26 to the zero state and, therefore, prohibiting the generators 37 and 38 At the same time, the “Operation and the“ Node 9 stop panel ”display lights up, indicating that the operator has completed the task.

The invention allows organizing a controlled educational process and, as a result, reducing the training time of management system specialists by 15-20%.

In addition, the proposed device allows improving the quality of operator control actions by eliminating automatism in his work, since the training process itself is aimed at developing conscious control actions by the trained operators. This increases by 25-30% the reliability of the control system in the loop of which the human operator operates.

The use of automatic localization of the location and nature of the operator’s error as the task is resolved allows the instructor to quickly identify with students the reason for their erroneous actions.

The reprogramming of tasks allows the operator to quickly change the training task without constructive modifications, which substantially widens the class of problems solved by the proposed device.

Claims (2)

1. A device for training operators, containing an operator console, the information output of which is connected to the response input of the response result generating unit, the reference and interrogation inputs of the comparison result are connected respectively to the information and synchronization outputs of the reference memory, the recording unit, the first information input of which is connected to The corresponding output of the memory block of standards, characterized in that, in order to expand the didactic capabilities of the device, a shaper code blocking and memory block of the response result, information input, operation mode input and output of which are connected respectively to the synchronization output, operation mode output and comparison blocking input of the response result generating unit, and the address input to the first information generator of the code generator connected to the first address the input of the pattern memory and the first information input of the response result generating unit, the second information input, the start output and the first installation output of which are connected from respectively to the synchronization output, the start input and the installation input of the code generator, the second information output of which is connected to the second address input of the memory of the standards, the information output of which is connected to the second corresponding input of the registration block, the third, fourth, fifth, sixth, resolution and installation the inputs of which are connected respectively to the output of the blocking node and the first indicator output, the second indicator output, the start output, the output of the comparison result and the first installation the output of the response result generating unit; the second installation output of the response result generation unit is connected to the corresponding inputs of the operator’s console and the blocking node, whose information input is connected to the synchronizing output of the operator’s console. 2. The device according to claim 1, characterized in that in it the response result generating unit comprises a comparison node, an OR element, first, second and third inverters, AND element, 2I-OR element, first, second, third, and fourth NAND elements, counter, start button, and reset button, the output of which is the first installation output of the unit and connected to the fourth trigger input, D input which is connected to the power bus, the C input is connected to the counter output, and the S input is connected to the start button output connected to the S input of the first trigger, the I and inputs of the second and third trigger and the first inputs of the second, third and fourth elements. NOT, the second inputs of which are connected respectively to the outputs of element 2И-OR, and the first IS element, and the first trigger, whose C input is the first information input of the block, and the input connected to the output of the first AND input, whose first input is connected to the output of the AND element, and the second input is the input of the result poll a unit connected to the first input of element 2I-OR, the second input of which is connected to the output of the second inverter, the third input to the output of the element OR, the fourth input to the output of the first inverter, and the fifth input is the input of blocking block connected to the input of the counter and the first input of the AND element, the second input of which is connected to the output of the comparison node, and the third input to the output of the OR element connected to the input of the third inverter and the input of the third trigger, the output of which is the first indicator the output of the block, and the C input is connected to the counter output connected to the C input of the second trigger, the D input of which is connected to the output of the third inverter, and the output is the second indicator output of the block, the output of the fourth trigger is C-entry counter - the second information input the block, and the outputs of the second, third and fourth elements AND –NE - the sync output, the output of the operation mode and the second installation output of the block, the output of the AND element connected to the input of the second inverter and is the output of the result block comparison, the input of the first inverter is connected to the output of the comparison node, the inputs of the first group of which are the input of the block reference, and the inputs of the second group and the inputs of the AND elements are the input of the response block. Ssyh.pulta2 C8: el.5 C9bix.Sn.5 Svy.5l.8 FIG. 2 OnWhm on WH.E. Na8h.5l.E1. ut 27 Nzx 7G Lg. Na8htS8, x ° UZL.Yu 7, Sfl.8 Uzi.Sh Thebes fig L CSbiK.SnA fie. five CSbix, 5l. 5 C Out 5l. fy From the out. 57. OnWh.bl.Z Fiyo.b . 7 Fig.8