SU1248034A1 - D-flip-flop - Google Patents

Abstract

The invention can be used in the construction of various devices for the transmission and processing of information. The purpose of the invention is to increase the noise immunity of the trigger. The device contains the major elements 1, 2 and 3 and the inverter 7. The introduction of the major elements 4, 5 and 6 and their connection with the trigger elements provided for blocking the change of the output state in the presence of an unstable signal at the information input in the time interval between potential changes at the clock input. As a consequence, the effect of a short-term (less than half-cycle clock time) interference will not lead to an erroneous change in the state of the trigger output. 2 il .. fig, /

Description

The invention relates to a pulse technique and can be used in the construction of various devices for transmitting and processing information.

The aim of the invention is to increase the noise immunity of a trigger by providing an output change state blocking in the presence of an unstable signal at the information input in the time interval between potential changes at the clock input, as a result of which the short-term (less than half-period clock signal) interference does not lead to an erroneous state change trigger output.

FIG. 1 shows the functional diagram of the D-flip-flop; in fig. 2 - time diagrams, according to his work.

D-flip-flop contains the first 1, second 2, third 3, fourth 4, fifth 5 and sixth 6 major elements, inverter 7, as well as clock (c) and information (d) inputs and one output. The input of the inverter is connected to the clock input. trigger and to the first input of the first major element r- .l, the second input of which is connected to the information input of the trigger and the first input of the second major element 2, the second input of which is connected to the output of the inverter, and the third input to the output of the second major element and the first the entrance of the third majority

element 3, the second input of which is connected to the third input and the output of the first major element, and the third input to the trigger output. The first input of the fourth major element 4 is connected to the output of the third major element and the first input of the fifth major element whose second input is connected to the output of the inverter 7, and the third input is connected to the output of the fifth major element 5 and the first input of the sixth major element, the second input which is connected to the output of the fourth major element 4 and its second input, and the output is connected to the output of the device and to the third input of the sixth major element 6. The third input of the fourth major electric ment 4 is connected, and a clock input of the flip-flop.

. D-trigger works in the following way.

o

20

The synchronization input of the D-flip-flop receives a sequence of pulse pulses, the inverse of which is present at the output of the inverter.

On the major elements 1 and 2, two E-type triggers are executed, the first inputs of which are supplied with the direct and inverse clock signals, respectively, and the second inputs are input information. Similarly, two E-triggers are made on elements 4 and 5, with the difference that the input information for them is the state) output 15 and the majority element 3. The final output signal is formed at the output of element 6, also type E trigger. The proposed scheme consists, as it were, of two type D triggers glued to each other, clocked by any syn-differential | a synchronizing signal for which inverter 7 is common for both the first and second trigger, and the local feedback of element 3 is replaced by global — from the output of the trigger to the third input of the element.

. Under the INF signal in FIG. 2, it is necessary to understand the initial information sequence, not distorted by interference, under the signal D-state of the information input of the trigger, to which the sequence of INF is distorted by interference.

The states of the outputs of elements 2, 3, 4, 5 and 6 at the initial moment of time (when the power is turned on) are considered uncertain, i.e. O or 1. The only element for which the initial state is uniquely is Jelement 1, the output of which is O due to the coincidence of the values of the information and clock signals at the initial moment of time. The next change in the clock signal removes the uncertainty from the output of element 2, since its two signals contain the same O. signals. The coincidence of the output states of the first and second elements uniquely determines the presence of O at the output of element 3. The change in the clock signal level does not change The state of element 1, since it is determined by feedback from its output to the third input.

The appearance of an output element 3 ensures installation in the element

35

40

45

50

ment 5, and during the next regular change of the clock signal - installation in O of elements 4 and 6, i.e. total trigger. The condition for setting a particular state at the trigger output is the presence of a stable definite signal at input D in the interval between two successive ones. other signal changes at the sync input.

Appearance 1 at the information input of the trigger acts on element 2, since at its other input there is also 1 output from the inverter. As can be seen from the diagrams, any subsequent changes in the state of the circuit are possible only with a change of the clock signal and the presence of a notch in the information signal does not affect the state of the outputs. The change of potential at the C input, in the presence of 1 at the D input, affects the output of element 1, and since the trigger executed on element 2 was previously recorded 1, it appears at the output of element 3 and then at the output element 4.

The stable state of the D input during the current half period of the signal ensures an unchanged state of the circuit elements and is a condition of writing 1 to the E flip-flop on element 5 and occurring 1 at the flip-flop output. : The potential change at the D-input directly affects That of elements J and 2, on the first input of which there is a signal corresponding to the information one. From the time diagrams (Fig. 2) it can be seen that the appearance of O on the D-input switches to O element 1, since this occurs during the negative zero loluperiod of the clock signal. Keeping O at the D input before changing the clock signal ensures switching to O of element 2 and, as a result, elements 3 and 5, but does not change the state of the trigger output, which requires another change of the clock signal to change. However, before this change at input B, potential 1 reappears, which leads to the return of elements I and 3 to the previous state and does not allow the trigger to switch to O at the next potential change at the synchronization input, during which it is again set to 1 element 5. The following quick signal changes at the D-input (O in 1 and again in O) repeat the described processes, and only the presence of a stable O for a duration of more than half a cycle of the clock signal will allow changing to an O signal at the output of the trigger.

Similarly, it does not perceive the trigger short-term occurrence 1 at the D-input, and its stable established value is tested by the circuit as correct and leads to switching the signal at the trigger output.

Thus, the main and only condition for switching the D-flip-flop is the presence of a stable signal at the information D-input, in the time interval between consecutive clock changes, and with an unstable signal at the D-input, i.e. the occurrence of both O and 1 during the time between clock changes, the trigger maintains the previous output state.

Immunity of the trigger to fast-changing signals provides a higher stability of the circuit to the effect of short-term interference,.

Claims (1)

Invention Formula D-trigger containing information input, clock input and output ,. - the first, second and third major elements and an inverter, whose input is connected to the trigger input of the trigger and to the first input of the first major element, the second input of which is connected to the information input of the trigger and the first input of the second major element, the second input of which is connected to the output inverter, and the third input to the output of the second major element and the first input of the third major element, the second input of which is connected to the third input and output of the first major element, and the third input of the third The major element is connected to the trigger output, characterized in that, in order to improve the trigger immunity, a fourth, fifth and sixth major element are introduced into it, the first input of the fourth major element is connected to the third major element and the first input The fifth major element, the second input of which is connected to the inverter output, and the third input is connected to the output of the fifth major element and the first input of the sixth major element, the second input of which is connected to the output of the fourth major element and its second input, and the output is connected to the output of the device and to the third input of the sixth majoritarian element, the third input of the fourth major element being connected to the clock input of the trigger. FIG. 2 Compiled by P. Smirnov Editor A, Lezhnina Tehred E. Chizhmar Proofreader M. Sharoshi 4140/57 Circulation 816 Subscription VNIIPI USSR State Committee on inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5 , Production and printing company, Uzhgorod, st. Project, 4