SU1220120A1 - Device for generating single pulses - Google Patents

Abstract

The invention relates to a pulse technique and can be used; In conversion devices,; processing and transmission of information. The purpose of the invention is to improve reliability. The device contains a ZK-flip-flop 1 and an element AND-NOT 2, the first input of which is connected to the bus 3 clock pulses and C-departure of the ZK flip-flop 1, bus 4 output pulses, D-trigger 5, D-input of which the connection is input bus 6 , C - input - via inverter 7 with a bus of 3 clock pulses. The introduction of the inverter 7 and the D-trigger 5 made it possible to generate pulses at the device input equal in duration to the clock pulses. The duration of the input pulses must be greater than the period of the following clock pulses. 1 silt i (L 7 | -o

Description

The invention relates to a pulse technique and can be used in devices for converting, processing and transmitting information.

The purpose of the invention is to increase the reliability of work.

The drawing shows an electrical functional circuit diagram of the device.

The device contains LC-trigger 1 and the element AND-NOT 2, the first input of which is connected to the bus 3 clock pulses and C-input JK-trigger 1, O - and K-inputs which are connected to its inverse output and the second input element And - NO 2, the output of which is connected to the ryn 4 output pulses j S –the trigger 5, J) —the input of which is connected to the input bus 6, C the input through the inverter 7 - to the bus 3 clock pulses, direct output - to the R-input ZK -trigger 1 and with the third input element AND-NOT 2.

The device works as follows

In the initial state on bus 6 is a logical zero. At the direct output of trigger 5, the zero potential, which keeps trigger 1 in this state, and also prohibits the passage of pulses from bus 3 through element 2. At the O - and K-inputs of trigger 1, as well as at the second input of element 2 potential of logical unit with inverse output of trigger 1.

When a logical unit appears on bus 6, the first pulse arrives; on bus 3 with its falling edge (negative), sets trigger 5 to one state, thereby removing the trigger zero signal 1 and opening element 2. Since the state

Compiled by T. Sokolov Editor O. Bugir Tehred A. Komarnitska Proofreader A. Zimokosov

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VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Branch PIP Patent, Uzhgorod, st. Project, 4

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220120

the trigger 1 does not change; a pulse is formed at the output of this element, the duration of which is equal to the duration of the pulses coming through the bus 3.

Upon termination of the pulse selected from the pulse train in busbar 3, trigger 1 switches to one state and the zero level from its inverse output blocks element 2 and itself via the D and K inputs. After that, the next pulse from the bus 3 does not pass through the element 2 to the bus 4.

Thus, at the output of the device, pulses of equal duration to clock pulses are formed.

To ensure the uninterrupted operation of the device, it is necessary that the duration of the input pulses be longer than the period of consecutive clock pulses.

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Claims (1)

Invention Formula A device for generating single pulses containing a DK trigger and an NAND element, the first input of which is connected to the clock pulse bus and to the C input of the LK trigger, the 3rd k input of which is connected to its inverse output and to the second input The NAND element whose output is connected to the output pulse bus, characterized in that, in order to increase the reliability of operation, an inverter and a D-trigger are entered into it, the D-input of which is connected to the input bus, the C input through the inverter is connected to the bus clock pulses, direct output - with the R input of the Ok trigger and the third in Odom NAND.