SU1246395A1 - Digital device for phase synchronization - Google Patents

Abstract

The invention relates to telecommunications and can be used in discrete information transmission devices. Noise immunity increases. The device contains a block of reference frequencies 1, analog-to-digital. Transform- Tejjb 2, block of addition-exclusion of pulses (BDII) 3, phase discriminator, (FD) -4, permanent memory (ROM) 5, memory register 6, two counters 7 and 16, accumulating adder .8, two threshold blocks 9 and 12, reversible counter 10, code converter 11, key 13, two inverters 14 and 15, four elements AND 17-20, code-frequency converter 21 and two elements OR 22 and 23, - in BDI 3, the phase of the adjustable oscillation is adjusted and compensated for

Description

Qi of the frequency detuning of the master and adjustable oscillations. T. arr. The output code of the PD 4 does not directly affect the address of the output signal taken from the ROM 5, but is pre-averaged. This reduces the effect of random non-information interference due to

The invention is related to telecommunication technology and can be used to create phase synchronization systems in digital transmission devices.

The purpose of the invention is higher noise immunity. °

The drawing shows a block diagram of a digital device, phase synchronization.

The digital phase synchronization device contains a block 1 of the reference frequencies, an analog-digital converter 2, a block 3 for adding and excluding pulses, a phase discriminator 4, a ROM 5, a memory register 6, the first counter 7, the accumulating adder 8, the first threshold unit 9, reversing counter 10, code converter 11, second threshold unit 12, key 13, first 14 and second 15 inverters, second counter 16, elements AND 17-20, code-frequency converter 21, first OR 22 and second OR 23 elements.

The device operates as follows.

The input signal is sampled at a frequency F0 and converted into a digital code using an analog-to-digital converter 2, the code from which is fed to the input of phase discriminator 4, the output of which is a signal determined by the phase difference of the input and reference signals. The reference signal is formed by a ROM 5 with recorded harmonic wave samples. The value of the signal at the output of the ROM 5 is determined by the address code specified by the first counter 7, which at the time of arrival of the clock pulse from block 1 is copied from the first counter 7 to the registrar 6, by noise and interference control, to the quality of the device operation. The goal is achieved by introducing BDI 3, memory register 6, counters 7, 10, 16, threshold blocks 9, 12, key 13, inverters 1A, 15, elements AND 17-20, converter 21, and elements OR 22 and 23. 1 Il .

the current value of the address code during the clock interval.

The phase mismatch code generated by the phase discriminator 4, the sign and value of which are determined by the ratio of the phases of the set and 1 of the generated oscillations, is fed to the accumulating adder 8 in each step, where it is added to its content. If there is a constant phase mismatch, the number arriving at accumulating adder 8 has one and. same sign. Therefore, after several cycles, the amount accumulated in accumulative adder 8 exceeds the threshold of the first threshold block 9 and the last produces one pulse.

Depending on the sign of the amount accumulated in accumulating adder 8, due to the presence of the first inverter 14, either the first element 17 and the second element 18 are open.

As a result, the pulse from the first threshold block 9, passed through the first IPI 2.2, or the second OR 23 elements., Goes to one of the control inputs of block 3 to the Add pulse input or Pulse exclusion input depending on the sign of the phase mismatch. In this case, a correction of 1 to 1 is made; the fluctuation is controlled.

The signal from the first threshold unit 9 also receives a reversible counter 10. Depending on the sign at the control input of the reversing counter 10, which is determined by the state of the sign output of the accumulating adder 8, the reversible counter 10 is turned on at Addition or Subtraction.

3

Reverse counter number code. 10 enters the second threshold unit 12 through a code converter 11.

Code converter 11 converts the inverse code of the number entered in the reversible counter 10 into direct. The reverse code is generated in the reversible counter 10 when it is operating in the subtractor mode and the number accumulated in it is negative. In this case, the high-order bit of the reversible counter 10 is used to control the code converter 11, since it carries information about the sign of the number accumulated in the reversible counter 9.

If the modulus of the number in the reversible counter 10, formed at the output of the code converter 11, is greater than the threshold value of the second threshold unit 12, the signal from the output: the second unit 12 opens the key 13. As a result, the input of the second counter 16 receives the clock pulses from unit 1 The code of the number, determined by the connection of the second counter 16, is fed to the control of the converter 21 to the clock input of which the reference frequency is fed from block 1. The pulses from the output of the converter 21 are next to the frequency proportional to the code of the number in the second sec. 1.6, go to the third AND 19 or the fourth And 20 elements.

Depending on the sign of the most significant bit of the reversible counter 10, which goes to the control input, the third element I 19 directly, and the input of the fourth element I 20 through the second inverter 15, one of the elements I is opened. Through the open element I, through one from the elements OR 22 or 23, the output signal of the converter 13 is fed to the control inputs Addition, Exclusion of block 3, to the MacTot compensator detuning of the master and reference oscillators.

Frequency detuning compensation leads to a decrease in the phase mismatch of the driving and tunable oscillations, as a result of the probability of accumulating negative and positive thresholds in the accumulator 8, and as a result, the number in v reversible counter 10 decreases. Change in the state of the second counter

95

sixteen

four .

occurs until the number in the reversible counter 10 becomes less than the trigger threshold of the second threshold unit 12. The key 13 is then closed, and the second counter 16 records the number determined by the frequency detuning of the generators.

The output code of the phase discriminator 4 does not directly affect the address of the output signal taken from the ROM 5, but undergoes averaging. As a result, the effect of random non-informative interference due to the influence of noise and interference on the performance of the synchronization device is significantly reduced.

In addition, for large frequency detunings in the proposed system, the time to synchronization is reduced due to the arrival at one or another input of block 3 (depending on the detuning sign) pulses from the output of converter 21 following a linearly varying frequency.

20 25 I Q

Claims (1)

Invention Formula A digital phase synchronization device containing an analog-to-digital. transducer, phase discriminator, reference frequency block, constant0 five This storage device (ROM) and accumulating adder, the analog-digital converter input being the device input and the output connected to the first signal input of the phase discriminator, the second signal input of which is connected to the output of the ROM, the first output of the reference frequency block is connected to clock inputs of the analog-digital converter, phase discriminator and accumulator adder, the output of the phase discriminator is connected to the input of the accumulator adder, characterized in that, for the purpose of noBbmie stability, two threshold blocks, a reversible counter, two inverters, four AND elements, two OR elements, an impulse addition-exclusion unit, two counters, a memory register, a code converter 5, a switch, and a code-frequency converter, the code the output of the accumulating adder is connected to the input of the first threshold unit, you-. 0 5-1246395 6 the progress of the sign bit accumulator, the code outputs of which are connected the adder is connected to the control input-to the inputs of the memory register, the code the house of the reversible counter, with the input the outputs of the memory register are connected to the first - the inverter and the first input, 5 corresponding to the inputs of the ROM, and the first clock element And, the output of the first input of the memory register - to the first the threshold block is connected to the counting output of the reference frequency block, the first the input of the reversible counter, the second inputs of the third and fourth elements of the first input element {, first and) are connected to, and the output of the second element AND, the second code-frequency gate, whose input inputs are connected to the output of the first the main inverter, the output of the first element counter, and the clock input of the socket AND connected to the first input is primary with the third output of the reference block element OR, the second input of which frequency, the input of the second counter is connected to the output of the third element, is connected to the output of the unit, the input of the key connects with the nepBb.iM input of the second OR element, frequencies, and the control input of the key is the second input of which is connected to the single input with the output of the second threshold the fourth element And, the blockblock, the input of which is connected to the first element of the Sh1I is connected to the 20th house of the code converter, the inputs to the code-first input of the add-on module are connected to the code chenyulus, the second input to the output of the reversible counter, the output connected by the output of the second element of the reverse discharge counter, OR, and the third input with the second output ka is connected to the input of the second inverter reference frequency, the output of the block is up to -25. ra and the second input of the third element Add-on exclusion of the pulses of the connecting-I, output: one inverter is connected to the second with a counting input of the first counter-input of the fourth element I.