SU1012448A1 - Device for evaluating channels and selecting optimal communication frequencies - Google Patents

Abstract

DEVICE-TO OTSENKIKANALOV and selecting the optimal communication frequency comprising series-connected input unit combining nonlinear multichannel receiver, the comparator elements connected in series block forming an adjustable reference signal consisting of a series-connected low-frequency signal generator, a multichannel high-frequency shaper reference signal and the attenuator unit , and a key, with the first additional output of a non-linear multi-channel receiver connected another input of the multichannel high-frequency reference signal generator, another input of the input additive unit is connected to the output of the key, and a control unit, the corresponding outputs of which are connected to the control inputs of the key, nonlinear multi-channel receiver, unit of reference elements, memory level and frequency numbers, the optimum frequency number selection block, the signal input of which is connected to the output of the memory block of interference levels and frequency numbers, and the output is connected to the first input of the control unit, about l and ch yu e s. In order to reduce the selection time, the connected to the outputs of the comparison element block and the other input of the attenuator block are the series-connected reversing and stopping unit, the code converter and the reversing block, and also connected between the second additional output of the non-linear multichannel receiver and others the input of the reversing unit a presetter shaper consisting of series-connected linear input amplifier , linear detector, and, a DC amplifier, the output of which is connected to another input of the input linear amplifier, and serially connected input selector of the maximum level, switch and output analog-digital converter, and the output of the DC amplifier is connected to the IS9 pa, the signal input of the memory block of noise levels and frequency numbers soy 4 is dinin with another output of the reversing unit, and the control inputs of the switch and the reversing unit are connected to The electronic outputs of the control unit, the second input of which is connected to one of the outputs; transform code 6.

Description

The invention relates to communication technology and can be used at communication stations to automatically estimate channels and control the optimal communication frequencies in adaptive systems. A device is known for estimating accumulation and selection of optimal communication frequencies, serially connected input addendum block, nonlinear multi-channel receiver, block of comparison elements, sequentially connected block of forming an adjustable reference signal consisting of a series-connected low-frequency signal generator, multichannel high-frequency former a reference signal and an attenuator unit, and a key, with the first additional output of a non-linear multichannel receiver connecting another input of the multichannel high-frequency driver of the reference signal, another input of the add-on block connected to the key output, and a control unit whose corresponding outputs are connected to the control inputs of the key, nonlinear multi-channel receiver, block of reference elements, block of noise levels and numbers frequency block, the optimal frequency selection block, the signal input of which is connected to the output of the memory block of interference levels and frequency numbers, and the output is connected to the first input of the control block Ci Od However, a known device has a long selection time. The purpose of the invention is to reduce the time of choice. To achieve this goal, a device for channel estimation and selection of optimal communication frequencies, containing a serially connected input addition unit, a nonlinear multichannel receiver, a unit of comparison elements, a serially connected unit (Normalizing the adjustable reference signal consisting of a series-connected low-frequency signal generator, a multichannel high-frequency driver of the reference signal and an attenuator block, and a key, with the first additional output of a non-linear multi-channel A separate receiver is connected to another input of the multichannel high-frequency driver of the reference signal, another input of the adder unit is connected to the output of the key, and a control unit whose corresponding outputs are connected to the control inputs of the key of the non-linear multichannel receiver of the unit of the comparator unit pa the number of interference levels and frequency numbers the block of choice of the optimal frequency, the signal input of which is connected to the output of the block by 1 interference levels and frequency numbers, and the sub-key output to the first input control locator, connected between the outputs of the comparison unit and another input of the attenuator unit (serially connected reversing and stopping signal conditioners, a code converter and a reversing unit, and also connected between the second additional output of the nonlinear multi-channel receiver and another input of the reversing unit, a presetter, and consists of a series-connected input linear amplifier, a linear detector, a constant amplifier voltage, the output of which is connected to another input-input linear amplifier, and serially connected input selector of the maximum level, switch and output analog-digital converter, and the input voltage of the constant voltage amplifier is connected to another input of the switch noise and frequency numbers are connected to another output of the reversing unit, and the control inputs of the switch and the reversing unit are connected to the additional outputs of the control unit, the second input e which is connected to one of the code converter outputs. Figure 1 shows the structural electrical circuit of the proposed device; Fig. 2 shows an embodiment of a non-linear multi-channel receiver; Fig. 3 shows an embodiment of the reversing unit; on. Fig. 4 is an embodiment of a block of reversing and stopping signal conditioners; Fig. 5 shows an embodiment of a block for selecting the number of the optimal frequency; Fig. 6 shows an embodiment of the control unit. A device for estimating channels and selecting the optimal communication frequencies contains a non-linear multi-channel receiver 1, an input addition unit 2, block 3 of the memory of interference levels and frequency numbers, a unit 4 of reverse and stop signal conditioners, a block 5 of reversal, a unit 6 of comparison elements, a block 7, selecting the optimal frequency number, the adjustable reference signal generating unit 8, consisting of the multichannel high frequency driver 9 reference signal, the attenuator unit 10 and the low frequency signal generator 11, The 12 pre-installation signal, consisting of the input linear amplifier 13, the output analog-digital converter 14, the switch 15, the linear detector 16, the constant voltage amplifier 1.7 and the maximum level input selector 18, control unit 19, key 20, code converter, antenna 21, antenna 22, Nonlinear multichannel receiver consists (Fig. 2) of frequency synthesizer unit 23, generator 24, frequency memory unit 25, preselector 26, first frequency conversion unit 27, second frequency conversion unit 28, unit 29 t Another frequency conversion, the first switch 30, the first channel filters 31, the second channel filters 32, amplifier blocks 33, the first frequency converters 34, the second frequency converters 35, the first channel amplifiers 36, the second channel amplifiers 37, the second switch 38, the detector block 39 and DC amplifier of automatic adjustment of the amplifier of the amplifier block 40 -gran5; 1chitel and the reference generator 41. 1 | of that, the reversing unit consists of (fig. 3) the element OR 42, the key 43, the buffer register 44, the switch 45, a reverse register 46 and a code converter 47, the block of reverse and stop signal conditioners block consists of (figure 4) buffer amplifier 48, buffer amplifier inverter 49, two flip-flops 50, -51 and code converter 52. In addition, the selection block the optimal frequency numbers consist (figure 5) of two multiplexers 53, 54, two elements And 55, 56, two inverters 57, 58 of the switch 59, two main registers 60, 61, two input registers 62, 63, five elements OR 64-68, trigger 69 and display unit 70, and the control unit consists of three races pulse breakers 71-73 of three elements AND 74-76, seven elements OR 77-83, three triggers 84-8.6, two delay elements 87, 88, block 89 of forming pulse signals, two drivers 90, 91 of pulse signals, a key 92 , the first switch 93, the driver 94. the signal of the original installation, the second switch 95 of the pulse generator 96.. The device works as follows. According to the commands given from block 19, the adjustment is made from 1 frequency to frequencies of generation and reception, respectively. After a known time determined by the transition processes, the command from block 19 to block 5 records the signal from the output analog-digital converter 14, after which the command from block 19 to block 10 transmits the signal from the reversing register of block 5 to block 10 and at the same time, the key 20 is opened. A modified in magnitude high frequency group signal is supplied to block 2, where it adds up to spatial interference from antenna 22. Filed at the first input to the non-linear multi-channel receiver 1 the reference signal and interference are amplified in it and converted into a low frequency spectrum, and then fed to block 6, where for each of the K channels, the narrowband and reflex filters, respectively, with bandwidth and reflection much smaller than the bandwidth of the corresponding channel filter, are produced accordingly the selection of the reference signal from interference and interference from the reference signal. Signal and interference are amplified separately by amplifiers. A polarity comparison signal or zero is removed from the nullorgan and fed to the corresponding block 4, where, respectively, the polarity of the incoming signal or the absence of it is generated by the corresponding pulse signals for reversing and stopping using, for example, a Chmidt trigger, 0 is formed when the comparison signal in algebraic value does not translate into some previously known, corresponding in sign THRESHOLDES. X levels. The generated signals are converted in code converter 21 into generalized reversing and stopping signals and fed to block 5, and the stop signal O is also fed to block 19. Reversing signals in block 5 are controlled, through the appropriate switch, to supply clock pulses to the corresponding reverse inputs the counting register, and the stop signal using the corresponding key stops the pulses to the inputs of the same register. The register signals are recoded and fed to the corresponding keys of block 10. Since the reversing signals of the register of block 5 are generally parallel to a digital signal, which by its significance corresponds to an effective level of interference, when this stop signal appears, the signal is read from the reversing register through a buffer register register and is fed to the record in block 3, where simultaneously from block 19 on the second input a command is given to write to the memory cell corresponding to the frequency of the communication. In addition, the stop signal supplied to block 19, after its termination, permits the command for rebuilding to the next frequency. The operation described is repeated at W frequencies. After that, according to commands sent simultaneously to blocks 3 and 7 via the second inputs, block 3 is read, and block 7 records the signal of the interference level. Simultaneously, in block 7, the signal of the frequency number is recorded, which is fed from the second input to the second input. After the first recording, a transfer command is sent to block 7, according to which the noise level signals and frequency numbers are read from the input registers and written to the main registers, For example, interference level signals and numbers of the second receiving frequency are recorded in the input registers, and commands of a bit comparison are given from block 19. The signal of the interference level with a lesser significance detected as a result of the comparison and the corresponding signal of the frequency number are written in the corresponding main registers or remain in them if they were in them before the comparison operation. - If, as a result of the comparison, it turns out that the signals of the levels of fur are equal in their significance, then the advantage is given by the principle of a signal in the main register. After the first comparison, block 7 introduces the signals of the interference level and the number of the third frequency, and then compares the signals of the interference levels of the newly entered and remaining in the main register. Such pairwise comparison is made for the interference levels of all frequency channels. The detected signal of the minimum noise level and the corresponding signal of the frequency number, at the command of block 19, are read and written to the corresponding storage registers, where they are stored until the end of the subsequent comparison cycle and used for visual indication. Thereafter, the cycle for evaluating interference levels and selecting the number of the described frequency begins. The signals of block 23 of FIG. 2) and generator 24 synchronized through block 23 are used as heterodyne signals. Block 23 operates on the basis of oscillations of a highly stable reference oscillator 41. The preselector 26 is tuned by signals from block 25 of frequency memory, which is controlled by commands c block 19. To rebuild block 23., receive frequency signals are used. with block 25. The first and second switches 30 and 38 are controlled from block 25, which is simultaneously a block of memory for modulating received signals. Depending on the type of modulation of the signals, the signal from the first switch OO is supplied either to block 40 or to filters 32. The signal from the output of first switch 30 is fed to driver 12, where it is limited, allocated by frequency discriminator and fed to channel filters 31, where filtering the channel signals, which are frequency-transformed by the respective converters 34, to the input of which from block 23 the heterodyning signals of the corresponding frequencies are supplied. Further, the signals are amplified by channels by amplifiers 36 and are fed through the second switch 38 to the input of input unit 2. Filters 32 filter channel signals of single-band modulation. These signals are amplified by the corresponding intermediate frequency amplifiers of blocks 3.3 and are converted by frequency in the respective converters 35, the second inputs of which are supplied with the corresponding heterodyning signals from block 23. Each block 33 of the channel amplifiers is covered by an AGC, the voltage regulating of which is generated in block 39 and supplied to the corresponding block 33 and to the corresponding input of the driver 12. In the second frequency converters 35, the channel signals are converted in frequency and further amplified. At the first input of block 4 (feed 4), signals of two polarities appear separately in time. Accordingly, the polarity of the signals is amplified by either the buffer amplifier 48 or the buffer amplifier inverter 49. Depending on this, trigger 50 is given or trigger 51. If the signal levels are insufficient for triggering or are absent, then both triggers are in the INITIAL state. Thus, the signals at the inputs of the code converter 52 are either equal to either a logical zero or a logical one is present on one of them. Depending on the presence of these signals, the code converter generates the reverse signal More (), Less () and Stop Stop signal (which are fed to the code converter 21, the signals from which are fed to the switch 45 (figure 3), the Switch 45, depending on the reverse signals, delivers a clock pulse from the key 43 to the first or second input of the reverse register 46, respectively, increasing the accumulation of elementary signals in it or decreasing. The signals of the reverse register 46 are fed to a code converter 47, where they are recoded and fed to b block 10. When the signal O is received, which is fed to the first input of the key 43 through the OR element 42, to the second input of the buffer register 44 and to the block 3, the key 43 closes and the supply is stopped

through the third clock input to the switch 45 and, therefore, to the reverse register 46. The stop signal for the buffer register 44 is the read signal and For block 3 the write signal. As a result, the information from the buffer register 44 is written to the corresponding memory cell of the block 3 In addition, the call 43 for some time is closed by a command from block 19 when the receiver is tuned to a different frequency for the transient time in it, as well as when the recording signal on the third input is fed to the reversing register 46 In this case, the register is in a preliminary state, which is determined by a signal inputted through the third input into the register.

Registers 61, 62 (Fig. 5) store the signals of the interference levels of two different frequency kangshov, and in registers 63, 60 g, the signals of the numbers of the corresponding frequencies. Comparison of signals is performed by re-supplying signals from registers 61 and 62 using multiplexers 53 and 54 to elements 55, 56. If the corresponding bit of main register 61 is less significant, the discharge from input register 62, t, e, is zero, it is inverted in inverter 58 into a unit and two units are supplied to the element 55 and a signal appears at its output, which through the element OR 65 enters the control unit 19, which stops the supply of control signals for the comparison of bits. If the bit from the input register is smaller,. than from the main register 61, the input register 62 and the element 56, the switch 59 / controlled by the control unit, transmits the signals to the trigger 51. If during the comparison the signal from the input register 62 is less than from the main register 61, the signal from element 56 through switch 59 enters the first input of trigger 69 and overturns it, in turn, through the element OR 66, a write signal is given through the second inputs to the main registers 60 and 61, and the same signal as the read signal is supplied through the element OR 64 at the third entrance to the input register 62 and the third input to input register 63,

The initial state of the flip-flop 84. (Fig. 6) allows the output pulse to be formed when the second input of the clock pulse is applied. This signal through the OR 78 element and the shaper 90 at the second input tilts the rsrigger 84, as a result of which the pulses through the elements | and 74 are stopped. In addition, the signal from the

, tel 90 through delay element 87, for example, a standby multivibrator, and through element OR 83 is fed to block 5, stopping the supply of clock pulses through the key there at the time of transients when tuning the receiver to a new reception frequency. In addition, the signal of the delay element 87 is delayed by the delay element 88. And through the OR element 83 prevents the clock impulses from being fed into the reversing register of block 5, and also serves as a recording signal when the reversing register is set to the pre-state by signals from the driver 12. In the initial state Trigger 84 is returned by a Stop signal from a code converter 21. The signal from the second input of the pulse distributor 71 appears after evaluating the level of interference at all frequencies and is fed to the first input of the element and 75, otorrhea with a corresponding signal from the trigger

85i, when a clock signal is applied, generates a pulse, KOTOEYLI on the first input, is fed to the pulse distributor 72, which is combined with the corresponding corresponding shapers of block 89 — the elements AND generates the transfer write-read-1 signals, the perenosa-2 (, the read signal from the main registers In addition, the unitary signal through the wires of the first output of block 89 is used as a signal of the receiver's receiving frequency number for supply to block 7. The trailing edge of the recording signal and the m itself prevents the signal of its state from forming the end of the comparison pulses from block 7 or, in terms of the importance of the compared signals in block 7, pulses from the pulse distributor 73. The falling edge of the recording signal tilts the trigger 86, which by its signal allows the formation of AND 76 from clock pulses of signals to the first input of pulse distributor 73, which is intended to feed signals to; multiplexer 6 of block 7. If in block 7, when compared in importance

1 the signals will turn out to be equal, then on you: during the pulse distributor 73

appears that through.

element OR 82 triggers trigger

86 in the initial state, which prevents the forcing of pulses by the element And 76. In addition, this one. the trigger returns to its initial state with a pulse of the end of the comparison with block 7, which is fed through the element OR 82. The signals from the OUTPUTS of the pulse distributor 72 through the element OR 80 lock the key

92, thereby preventing the random stop signal from being sent to the trigger 84 during the npoiiecca selection of the number of the optimal frequency. By the signal jC of shaper 94, the corresponding blocks and circuits are set to the initial state after switching on.

The technical and economic efficiency of the proposed device consists in the fact that due to the successive servicing of several adaptive receivers, each of which has its own group of reception frequencies from which the optimum ones are extracted, savings are achieved in hardware.

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Claims (1)

DEVICE FOR THE ASSESSMENT OF CHANNELS AND THE CHOICE OF OPTIMAL COMMUNICATION FREQUENCIES, comprising a series-connected input addition block, a non-linear multichannel receiver, a block of comparison elements, a series-connected block of formation of an adjustable reference signal, consisting of a series-connected generator of a low-frequency signal, a multi-channel high-frequency shaper of the reference signal and a block of , and the key, and the first additional output of the nonlinear multichannel receiver is connected to other the input of the multi-channel high-frequency driver of the reference signal, the other input of the input addition block is connected to the key output, and the control unit, the corresponding output of which is connected to the control inputs of the key, non-linear multi-channel receiver, block of comparison elements, memory block of noise levels and frequency numbers, block number selection optimal frequency, the signal input of which is connected to the output of the memory unit t. · · Levels of interference and frequency numbers, and the output is connected to the first input of the control unit, excluding. I mean that, in order to reduce the time of choice, it includes the series-connected block of the reverse and stop signal shapers, the code converter and the reverse block, connected between the second additional output of the nonlinear multichannel receiver and included between the outputs of the block of comparison elements and the other input of the block of attenuators the other input of the reversing unit shaper preset signals, consisting of series-connected input linear amplifier, line a detector, a constant voltage amplifier, the output of which is connected to another input of an input linear amplifier, and a maximum level selector input selector, a switch, and an analog-to-digital converter, connected in series, the output of a constant voltage amplifier connected to another input of the switch, the signal input of the noise level memory block and. frequency numbers are connected to the other output of the reversing unit, and the control inputs of the switch and the reversing unit are connected to additional outputs of the control unit, the second input of which is connected to one of the outputs of the code converter. '' SU „., 1012448