RU2039415C1 - Device for separation of transmission and receipt direction in duplex communication systems - Google Patents

Abstract

FIELD: electric communications. SUBSTANCE: device has input unit 1, level conversion unit 2, differential system 3, analog-to-digital converter 4, routing unit 5, memory units 6, 10, oscillator 7, computing unit 8, adder 9, control unit 11, threshold unit 12, flip-flop 13, corrector 14. EFFECT: increased functional capabilities. 3 cl, 2 dwg

Description

 The invention relates to telecommunications.

 A device is known that includes a serially connected input unit, a switch, a first digital-to-analog converter, an analog-to-digital converter, a first memory block, a subtractor, connected by a second input to the output of an analog-to-digital converter, an adder, a second memory unit connected by an output to the second input of the adder as well as a second digital-to-analog converter, address generator and generator.

 The objective of the invention is to increase the noise immunity of received messages.

 In FIG. 1 is a structural electrical diagram; FIG. 2 diagram of the first memory block.

 The device comprises an input unit 1, a level conversion unit 2, a differential system 3, an analog-to-digital converter 4 (DAC), an addressing unit 5, a first memory unit 6, a generator 7, a subtraction unit 8, an adder 9, a second memory unit 10, a unit 11 control, threshold block 12, trigger 13, corrector 14.

 The addressing unit comprises a random access memory 15, a parallel register 16, an adder 17, a counter 18 with preliminary recording, a serial register 19.

 The first memory block contains random access memory 20, parallel register 21, key 22.

 The device operates as follows.

 Four simultaneous processes can be distinguished, which, in turn, are interconnected.

 The first process is the formation of the transmitted signal. This operation is carried out cascaded by an input 1 unit, a level conversion unit 2, and a differential system 3, which transmit signals of their own transmission in the transmission direction.

 The second process is the formation of the address for the normal operation of the device. This operation is carried out using the addressing unit 5, where the constituent parts include a serial register 14, random access memory 15, parallel register 16, adder 17 and a counter with a preliminary record 18.

 The third process is the compensation of the signals of its own transmitter in the receive path. It is carried out using a differential system 3, which transmits signals from the communication line and attenuates the signals of its transmitter, corrector 14, analog-to-digital converter 4, memory block 6 and block 8.

 Finally, the fourth process is to restore the shape of the received signal. It is carried out using an adder 9, a second memory block 10, a threshold block 12, and a trigger 13.

 All of the above processes are controlled by the control unit 11 in conjunction with the generator 7.

 Now consider the processes listed above in more detail.

 So, the first process, as mentioned earlier, is necessary for the formation and simultaneous binding to the clock frequency of the signal processing to be transmitted. The input signal is input to input 1 of the block, which is essentially an ordinary D trigger. The clock input of the input unit 1 receives the clock clock from the output of the generator 7. The signal at the output of the input unit 1 repeats the input signal, however, its appearance is strictly synchronized with the clock frequency. Next, the transmitted signal enters the block 2 level conversion. For a two-level signal, the level conversion unit 2 represents a comparator, to the second input of which a threshold value is supplied. When a logical unit is formed at the output of the input block 1, the voltage + U will be at the output of the level conversion block 2. If a logic zero is generated at the output of the input unit 1, then the output signal of the level conversion unit 2 will be -U. Next, the transmitted signal is fed to the input of the communication line through the differential system 3 and at the same time due to the non-ideal parameters of the differential system 3 in the receiving path. This is where the first process ends.

The second and third processes proceed interconnectedly. Let's consider them in more detail. So, at the output of the differential system 3 it observes the sum of two signals: received from station B and its own, flowing into the receiving path. The total signal is fed to the input of the corrector 14, which corrects the amplitude-frequency and phase-frequency distortions of the communication line (hereinafter, AFI and PSI). The corrector 14 eliminates the AFI and the PSF of the received signal. For its own transmitted signal, the corrector 14 distorts the shape of the spurious signal, however, due to the linear nature of the work of the corrector 14, this will not affect the further work of compensation of the transmitted signal. To compensate for the signals of its own transmitter in the receiving path, the law of relativity is used. According to this law, if you know the sequence of transmitted symbols, then the interference from the signals of your own transmitter in the receive path can be compensated by subtracting it at adjacent clock intervals. Let the signals in the form of S (K ₁ Δt), S ₂ (K ₂ Δt) be transmitted at the output of input block 1. S _n (K _n Δt). Hereinafter, K Δt means a discrete time instant. From the transmitted signals at the output of the A / D converter, we observe an interference equal to
P ₁ (K ₁ Δt) S ₁ (K ₁ Δt) * g _ds (K Δt) * * L _cor (K Δt) (1)
P ₂ (K ₂ Δt) = S ₂ (K ₂ Δt) * g _ds (K Δt) * L _cor (K Δt)


P _n (K _n Δt) S _n (K _n Δt) * g _ds (KΔt) * L _cor (K Δt) Here g _ds (K Δt) is the impulse response of differential 3 in the signal transmission path,
L _cor (KΔt) impulse response of the corrector 14.

Due to the linear nature of the impulse response of the differential system 3 and the corrector 14, we can say that the transmitted signal S ₁ (K ₁ Δt) corresponds to interference P ₁ (K ₁ Δt). Similarly, the signal S ₂ (K ₂ Δt) corresponds to interference P ₂ (K ₂ Δt), etc. It should be said that the parameters of the differential system 3 and the corrector 14 can change in time due to changes in the parameters of the communication line. This will lead to the fact that the value of the interference samples P _i (KΔt) will change. However, according to the law of relativity, the magnitude of these changes at adjacent clock intervals will be small. In fact, let us transmit the signal S ₁ at times K ₁ Δt and K ₁₀ Δ t. In the first case, the output of the ADPC will be a noise equal to P ₁ (K ₁ Δt), and in the second case, P ₁ (K ₁₀ Δ t) P ₁ (K ₁ Δt) + σ ₁ . The value of σ ₁ just due to the instability of the communication line. Similarly, if the signal S ₁ is again transmitted to the next K ₂₀ Δt, then at the output of the ADC 4 there will be a noise equal to P ₁ (K ₂₀ Δt) P ₁ (K ₁₀ Δt) + σ ₂ , etc.

Then, according to the law of relativity, the compensation of the signals of its own transmitter in the receive path will consist of subtracting the signals at adjacent clock intervals. For these purposes, memory block 6 and block 8 are used. So, let the ADC 4 output at the i-th clock interval during transmission (for example) observe a signal equal to
L _i (K _i Δt) П ₁ (K _i Δt) + y _i (K _i Δt) (2) Here y _i (K _i Δt) is the countdown of the received signal.

According to what was said above, using address block 5, we must find in memory block 6 that memory cell where interference P1 was previously recorded. Let such a cell be found where the signal equal to
L _m (K _m Δt) П ₁ (K _m Δt) + y _m (K _m Δt) (3) Then at the output of block 8 we will have a signal equal to
M _i (K _i Δt) L _i (K _i Δt) L _m (K _m Δt) y _i (K _i Δt) t _m (K _m Δt) (4) As can be seen from (4), there is no amount of interference from own transmitter.

 We show how the desired memory cell is indicated for memory block 6 from address block 5.

To accomplish this task, the output signal of the input unit 1 enters the addressing unit 5 at the input of the serial register 19. In this case, the sequence of zeros and ones that is transmitted to the side of station B is simultaneously delayed in the serial register 19. Thus, the output signal of the serial register 19 is the set of zeros and ones that are transmitted at the current moment of time and at previous transmission clocks. The operation of delaying the transmitted signal in the serial register 19 is essentially the formation of signals S ₁ , S ₂ . S _n for controlling the memory unit 6, since each sequence of zeros and ones has its own interference from its transmitter at the input of the receiver. If we denote by N the number of bits at the output of the serial register 19, and by M the number of address bits of the memory block 6, then M> N. The remaining K bits (K M-N) are formed using random access memory 15, parallel to register 16, the adder 17 and a counter with a preliminary record 18. Let us show how this is done.

Let the transmitted signal stored in the serial register 19 has the form 10001011 (N 8) at time t ₁ . At the next time t ₂ in the serial register 19, all information is shifted one step to the right, while the least significant bit is lost. If, for example, a logical zero was transmitted, then the output of the serial register 19 will be a signal equal to 01000101. To control the operation of the operational storage unit 15, code combinations are used that are shifted one bit to the left relative to the combinations received at the input of the memory unit 6. So, in moment t ₁ in the direction of the memory block 6 receives a signal 10001011, and the address combination of RAM 15 receives a code combination 01000101. This sequence of actions prepares RAM 15 for operation when the next code combination appears. The capacity of the RAM 15, parallel to the register 16, the adder 17 is the same and equal to K bits.

Let at the first time t ₁ RAM 15 was zeroed. Then, with the appearance at time t _1, code combinations 01000101 from RAM 15 with this address are read zero and written by the signal from the output of the control unit 11 to the parallel register 16. Next, the signal from the output of the parallel register 16 is added to the adder 17 with one and written to the RAM 15 at the same address 01000101. With the beginning of the time interval t _{2, the} signal from the parallel register 16 is recorded in the counter 18, which under the action of clock pulses begins to change its state from the previously set state. For example, at time t ₂ , 0. 0 is written to counter 18. After this, the state of the counter changes as follows: 0,1,2.15. If the counter 18 is pre-recorded "1", then the state of the counter 18 will be as follows: 1,2,3.15,0.

In the event of a combination of 01000101 appearing at some regular t ₁ clock interval at the address input of RAM 15, the unit is considered to be from RAM 15, written to parallel register 16, and the number "2" will be written to RAM 15, etc. Thus, using RAM 15, parallel register 16, and adder 17 for different code combinations, the contents of RAM 15 are increased by one. Upon reaching state IIIl in RAM 15, “0” is written in RAM 15 (IIII + 0001 0000, transfer is discarded). This operating procedure allows you to adapt to the parameters of the communication line. So, at time t ₁ , code combinations 010001010000, 010001010001, 01000101111111 are received at the address inputs of memory block 6 at the time t ₂ , code combinations in the form 010001010001, 010001010010, 010001010000 are received at the address inputs of memory block 6.

As can be seen from this description, N senior bits at time intervals t _i -t _{i + 1 are} unchanged, and the remaining "K" bits change. Since the senior bits are unchanged, then the interference P _i at the output of the ADC 4 will also be approximately the same. From the first memory block 6, at the first address generated from the addressing block 5, the contents of the corresponding memory cell are first read.

In the cell with the next number, write the new interference value plus the received signal count. And further from the remaining cells information is only read. Then at the output of the memory block 6 appear at the first moment of time P ₁ (K ₁ Δt) + y ₁ (K ₁ Δt), at the second moment zero (recording information), in the third P ₁ (K ₃ Δt) + + y ₃ ( K ₃ Δt). in the sixteenth P ₁ (K ₁₆ Δt) + y ₁₆ (K ₁₆ + Δt). With this appeal to the memory block 6, the first members of the above sequence are the same, and the second members are random. Thus, the output of the subtractor 8 will be a signal in the form
y _i (K _i Δt) t ₁ (K ₁ Δt); y _i (K _i Δt) y ₃ (K ₃ Δ t);
y _i (K _i Δt) y ₁₆ (K ₁₆ Δt) (5)
When reading the information, the key 22 is closed, the signal from the outputs of the RAM 15 through the common bus goes to the inputs of the parallel register 21. The signal is written to the parallel register 21 by the signal from the output of the control unit. In the case of recording information in the RAM 20, the key 22 is opened and the write signal passes through the shared bus to the inputs / outputs of the RAM 20. The operating modes of the key 22. The RAM 20 and the output register 21 are strictly synchronous and are controlled by the signals from the output of the control unit and the addressing unit. On this, the second and third stages end.

The fourth stage is designed to restore the shape of the received signals. Since the device is designed to separate two-level signals, in series (5), if y _i (K _i Δt) is a positive value [y _i (K _i Δt)> 0] then the whole sequence has either a positive value or zero value when terms are the same in magnitude and sign. Using the adder 9, the second memory block 10 is a summation of all components from the output of the subtractor 8.

[y_i(K_iΔt)-y_j(K_jΔt)]
Таким образом, если отсчеты принимаемого сигнала y_i не имеют постоянной составляющей, то знак величины Q однозначно характеризует знак принимаемого сигнала. Сложнее обстоит дело, если каждый отсчет принимаемого сигнала имеет постоянную составляющую. Тогда выходной сигнал сумматора 9 сравнивается с пороговым значением в пороговом блоке 12. Величина порога в пороговом устройстве выбирается из соотношения
Р 2^к˙С Здесь С величина постоянной составляющей принимаемого сигнала
Р значение порога
к- количество разрядов счетчика 18
(к М N)
Тогда, если Q > P, то в триггер приема 13 записывается логическая единица. Если же Q < P, то в триггер приема 13 записывается нуль.The output signal of the adder 9 is described by the expression
Q

[y _i (K _i Δt) -y _j (K _j Δt)]
Thus, if the samples of the received signal y _i do not have a constant component, then the sign of Q uniquely characterizes the sign of the received signal. The situation is more complicated if each sample of the received signal has a constant component. Then the output signal of the adder 9 is compared with the threshold value in the threshold block 12. The threshold value in the threshold device is selected from the relation
P 2 ^to ˙C Here C is the value of the DC component of the received signal
P threshold value
to the number of bits of the counter 18
(to M N)
Then, if Q> P, then the logical unit is written into reception trigger 13. If Q <P, then zero is written to receive trigger 13.

 Thus, the output signal of the receive trigger 13 uniquely characterizes the sign of the received signal and is issued to the message consumer.

The device is adaptive. Changing the parameters of the communication line leads to a change in the interference patterns, which are recorded in the memory block 6. Thus, after several transmission cycles, due to changes in the interference patterns P _i from the signals of the own transmitter, their compensation will be the same.

Claims (3)

 1. A device for separating transmission and reception directions in duplex communication systems, comprising a generator, the first output of which is connected to the first input of the input unit, the input of the analog-to-digital converter and the first inputs of the first and second memory blocks, the outputs of the latter are connected respectively to the first inputs of the subtraction unit and the first memory unit, the second input of which is connected to the output of the adder, the second input of which is connected to the output of the subtraction unit, characterized in that the control unit, the addressing unit, the threshold are introduced a second unit, a trigger, a level conversion unit, a differential system and a corrector connected in series, the first and second outputs of the control unit being connected to the first and second inputs of the addressing unit, the first and second outputs of which are connected to the third and fourth inputs of the first memory unit, the fifth input of which connected to the third output of the control unit, the fourth output of which is connected to the third input of the second memory unit and the first input of the trigger, the output of which is the output of the device, and the second input is connected to the threshold unit, the input of which is connected to the output of the adder, the output of the corrector is connected to the second input of the analog-to-digital converter, the input of the level conversion unit is connected to the output of the input unit, the second output of the generator is connected to the input of the control unit.  2. The device according to claim 1, characterized in that the addressing unit comprises an adder and a serial register connected in series, a random access memory, a parallel register and a counter with preliminary recording, the parallel register output being connected to the adder input, the second inputs of the serial register, random access memory the device and the parallel register are combined and are the first input of the addressing unit, the second and third inputs of which are respectively the second counter inputs with recording and serial register, and outputs the second output of the serial register and counter with preliminary recording.  3. The device according to claim 1, characterized in that the first memory unit contains a series-connected key and output register, as well as random access memory, information input-output connected to the input of the output register, the output of which is the output of the first memory unit, the first, second , the third, fourth and fifth inputs of which are connected respectively to the first input of the key, combined by the second inputs of the random access memory and the output trigger, the third and fourth inputs of the operational memory a common device and the combined second input of the valve and the fifth input of random access memory.

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