SU1225034A1 - Digital phase synchronization device - Google Patents

Abstract

The invention relates to telecommunications and can be used in devices for the transmission of discrete information. Noise immunity increases. The input signal through the A / D converter 1 is fed to a digital phase discriminator 2. In this block, the phases of the driving oscillation and the oscillation generated by the functional converter (AF) 12 are compared. The FC 12 is a memory device in which the codes of discrete samples of the harmonic oscillation are written in the form of tables of values sin and cos. The address of the desired value BHxojciHoro of the signal of the FP 12 generates a reversible counter (PC) 10. The pulses of the 15 clock pulses in the PC 10 rewrite the number from the adder 11. The adder 11 accumulates the previous value of the PC 10 code with the contents of the PC 14 into which from block 18 setting the start code through block 17 of the code census enters the code of the nominal increment of the address. The code of the phase mismatch from the digital phase discriminator 2 is fed to the cumulative adder (HC) 4. When the content of the HC 4 exceeds a certain value, the threshold unit 3 gives them 9 M g to to eat oo 4

Description

pulse. This pulse through the delay element 5 is fed to the keys 7 and 8 and passes to the corresponding inputs of the PC 10 and the averaging unit 9 through the key that is open. The control signal, depending on the sum sign in HC4, is supplied to key 7 directly, and to key 8 via the inverter 6.

one ,

The invention relates to telecommunications technology and can be used to create phase synchronization systems in devices for the transmission of discrete information.

The purpose of the invention is to improve noise immunity.

The drawing shows a structural electrical circuit of a digital phase synchronization device.

The digital phase synchronization device contains an analog-digital converter 1 (ADC), a digital phase discriminator 2, a threshold unit 3, a cumulative adder 4, a delay element 5, an inverter 6, the first and second keys 7 and B, averaging unit 9, the first reversible counter 10, adder 11, functional converter 12, control unit 13 second reversible counter 14, clock generator 15 control block 16, code rewriting block 17, initial code set block 18.

In the functional converter 12, which is a permanent memory device, the codes of sampled samples of the harmonic oscillation are recorded. The synchronization task is reduced to determining at the clock moment of time the address of the desired reference, i.e. reference harmonic oscillation equal to the value of coherent with the master. Since the frequency f of the clock pulses of the generator 15 clock pulses and the nominal frequency f of the driving oscillation are known in advance, the ratio between the periods of these frequencies is advantageous

lr,

And the number N of sampled values

As a result, the PC 10 adjusts the reference address. At a constant sign of the phase mismatch, the overflow pulse from the averaging unit 9 goes to PC 14, thereby changing the step of the nominal increment. This is equivalent to changing the frequency of the tunable oscillation. 1 il.

(one)

of the samples recorded in the functional converter 12 and making up the full period T of the harmonic oscillation, you can calculate the nominal increment of the address N, the desired reference of the functional converter 12 that occurs in each cycle:

T ". I x u i

NrT N -f-N ,. IM, r

Thus, the address 2dr, Dg of the required reference in the rth clock point of time can be calculated as

e.M in “D- (,

where is the address of the previous count, i.e. the count that appears in the (r-1) -th clock point in time, the sign {... (mod N) means that addition in curly braces is performed modulo N 2.

-

This circumstance is the basis of the operation of the proposed device. The values of N determined by expressions (1) and (2), and Chвыi H ® take into account the actual phase shift and frequency deviation of the oscillating wave from its nominal value f, taken in formula (1). These factors are monitored using a phase locked loop system.

Digital device phase synchronization works as follows.

The input signal is sampled and transformed into a digital code by means of ADC 1. With the help of digital phase discriminator 2, the phases of the driver and the oscillation circuit are compared to and in

J

depending on their ratio, a phase difference signal is generated, represented as a code Zg r j. The samples of the oscillations generated by the circuit are taken from the functional converter of the phase code to the instantaneous value codes of the output signal of the functional converter 12, which is a permanent storage device with a sine or cosine value table written to it. In this case, the address of the desired output signal, which determines the phase produced by the oscillation circuit, is the code recorded in the first reversible counter 10. The formation of this code is carried out in the following way. In block 18, the initial code setting stores the code of the nominal increment of the address N, the desired reference of the functional converter 12, calculated using formula (1). When turned on

the equipment on command from the control block 16 through the block 17 census block records this code into the second reversible counter 14. In each clock cycle, i.e. with the arrival of each clock pulse from the generator 15 clock pulses, the first pie-version counter 10 is accumulated as a result of adding modulo Nj the number recorded earlier in the first reversing counter 10 with the second reversible counter 14, i.e. the algorithm prescribed by formula (2) is implemented. The number in the first reversible counter 10, as noted at the beginning, is the address of the output signal of the synchronization device taken from the digital transducer 12 of the synchronization device and fed to the digital phase discriminator 2. Depending on the ratio of the phases of the driver that is generated by the oscillation circuit. Normalized by the digital phase discriminator 2 The phase error code Zg can have a different sign and meaning. In each cycle, this code goes to cumulative adder 4, where it is added to the contents of this cumulative adder. When there is a constant phase mismatch, the number Zg in the prevailing majority of cases has the same sign. Therefore, after several cycles, the amount is.

25034

accumulated in accumulative adder 4, exceeds the threshold of threshold unit 3 and the last one pulse is ablaze. Depending on the 5 characters accumulated in the cumulative adder 4, due to the presence of the inverter 6, it opens from the keys 7 or 8. As a result, the impulse from the threshold block 3 passes through

10, the delay element 5 and through the public key 7 or 8 enters the counting input of adding or subtracting the first reversible counter 10 and, by that, the phase 1 of the circuit’s 15 output signal is corrected by one step (the address of the reference taken from the functional converter 12 changes by one. Thus, in the proposed device is implemented proportional

20 adjustment loops. The delay element 5 is needed in order to eliminate the possibility of failures of the first reversible counter 10, associated with the simultaneous arrival of a pulse on

25, its computational input of addition and subtraction and rewriting of the parallel code from the matrix 11. In addition to the counting input of the addition and subtraction of the first reversible counter 10, each correcting pulse for the proportional control loop enters the input of the addition or subtraction of the averaging unit 9. If there is a constant the sign of the phase mismatch,

caused, for example, by the divergence of the frequencies of the driver and the adjustment I

At the output of the first and second keys 7 and 8, the same input of the averaging block 9 constantly arrives at 0. As a result, the latter overflows and an impulse appears at one of its outputs, in accordance with the overflow sign. which goes to the counting input of the subtraction or addition of the second reversible counter 14. As a result, the number in the second reversible counter 14 changes to. one or another side on a unit- 0 tsu. This means that the step of the nominal increment per step ad- changes. the race of the tunable oscillation N,, which is physically equivalent to the change in the frequency of the tunable oscillation. 5 The averaging unit 9 and the second reversible counter 14 perform in the proposed device the functions of an integrated control loop. The control unit 13 serves to restore the operability of the circuit if, as a result of interference, the number in the second reversible counter 14 (nominal increment Nj) is severely distorted. The control unit 13 monitors the state of the bits of the second reversible counter 14 and, if the code deviation in the second reversal counter 14 is exceeded from N, the permissible (set in the design) value, raises the signal to the control unit 16. On this signal, control block 16 reopens the code census block 17, and the nominal value of the number N is recorded in the second reversible counter from block 18.

Claims (1)

Invention Formula A digital phase synchronization device containing an analog-to-digital converter (ADC), the output of which is connected to the first signal input of a digital phase discriminator, to the second signal input of which the output of the function converter is connected, and the output of the digital phase discriminator connected to the input of the cumulative cy “atop” to the clock input of which, as well as to the clock inputs of the digital phase discriminator and the ADC, the output of the geyrator of clock pulses is connected, the input of the ADC is the input devices, characterized in that, in order to increase the noise immunity, a threshold unit, a delay element, two keys, an inverter, an averaging unit, a unit L. Edward Povkhan Order 1965/60 Compiled by G. Lerantovich Tehred I. Gaidosh Proofreader E. Sirohman Circulation 624 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nabo. Up to 4/5 Production and printing company, Uzhgorod, Projecto st., 4 5 0 5 0 5 o 5 0 control unit, control unit, code setting unit, code rewriting unit, two reversible counters and an adder, the output of which is connected to the input of the parallel code of the first reversible counter, to the addition and subtraction inputs of which, as well as to the addition and subtraction inputs of the averaging unit outputs, respectively, of the first and second keys are connected, while the code output of the cumulative adder is connected via a series-connected threshold unit and a delay element to the signal inputs of the first and second keys, and the output is sign times The accumulator adder is connected to the control input of the first key directly and via an inverter to the control input of the second key, and the outputs of the averaging block are connected to the addition and subtraction inputs of the second reversible counter, the output of which is connected to the first input of the adder and through the control unit connected in series control unit - to the control input of the code rewriting unit, to the code input of which the output of the initial code setting unit is connected, and the output of the code rewriting unit is connected to the input the parallel code of the second reversible counter, to the clocking input of which the second output of the control unit is connected, while the output of the clock generator is connected to the clocking input of the first reversible counter, the output of which is connected to the second input of the adder and the input of the functional converter.