SU1246394A1 - Two-step parallel-serial regenerator - Google Patents

Abstract

FIELD OF THE INVENTION The invention relates to digital radio and can be used in a trunk short-circuit system. Out Bitl In r kovolovoy radio. It is true that signal regeneration is correct. The device contains p-one-stage regenerators 1, p error analyzers (AO) 2 parallel test signals, AO 3 sequentially test signals, p-phase pulse distributor 4, frequency divider by two 5, pushbutton switch 6, pulse generator 7, multiplexer 8 , shift register 9, nine triggers 10-18, four frequency dividers 19-22, two modulo-23 adders 23 and 24, decoder 25, four pulse counters in parallel with (L Od CO; o

Description

one

26-29, reversible counter 30, two elements OR 31 and 32, twelve elements AND 33-44, six delay elements 45-50, add-subtractor 51 and phase discriminator 52, If it is necessary to transmit information in the shortest time the irregularity of the group time of deceleration to parallel channels, it is proposed to use the results of preliminary testing

"

The invention relates to digital radio communications and can be used in a system of backbone shortwave radio communications.

The purpose of the invention is to increase the accuracy of: signal regeneration.

The drawing shows the structure, on the electrical circuit of a two-stage parallel-serial regenerator,

The two-stage parallel-serial regenerator contains n single-stage regenerators of pa-specific test signal error analyzers, a 3-error test analyzer of a serial test signal 4, a 4-pulse n-phase distributor, a divider of 5 frequencies into two, a pushbutton switch 6, a generator of 7 pulses , multiplexer 8, shift register 9, first 10, second 11, third 12, fourth 13, fifth 14, sixth 15, seventh 16, eighth 17 and ninth 18 flip-flops, first 19, second 20, third 21 and fourth 22 dividers frequency, the first 23 and the second 24 Su 1mator p about module two, decoder 25, first 26, second 27, third 28 and fourth 29 pulse counters, reversible counter 30, first 31 and second 32 elements OR, first two eleventh And 33-44, first 45, second 46, the third 47, the fourth 48, the fifth 49 and the sixth 50 delay elements, the add-subtract block 51 and the phase discriminator 52,.

The device works as follows.

46394

lines. Such testing both specifies the transmission of information with a given quality and using test results to determine the correct phase of the clock frequency of the strobe pulses, even in the case of such signal distortions, in a line where the grouping criteria can be performed, but parallel to signal conversion is performed incorrectly. 1 il.

0

"five

five

35

25

The information inputs of single-stage regenerators 1.-1 receive n-synchronous digital sequences shifted relative to each other in accordance with the characteristic of the group delay time of the entire radio path. In each single-stage regenerator 1, the clock frequency of strobe pulses, which provides for each regenerator, is allocated registration of incoming discrete information

The task reference generator is a generator of 7 pulses.

In the p-phase distributor of 4 pulses, n phase phases are formed. To quantize the strobe phase of all n-one-stage regenerators 1 independently of each other at multiplexer 8, search for the optimal phase frequency f -f., For optimal recording of information from all single-stage regenerators 1 into shift register 9 (with parallel input and buffer) is carried out by two criteria. According to the first criterion, the average phase position is calculated between the clock pulses of all n-one-stage regenerator ov

In order to obtain a minimum phase error, all strobe pulses are quantized by high-frequency pulses of time distributed with the number of channels n at the output of one-stage regen; 1 rators. At the output of multiplexer 8, p-sequences of strobe pulses in clock

points of the Kf frequency, where each channel corresponds to its own phase of the Kf frequency,.

In the fourth counter 29, the phase distribution of strobe pulses is conducted depending on their phase shift with respect to the strobe pulse, the phase position of which is conventionally taken as the initial position. The convention of the numbering of strobe pulses at the first moment is determined by the arbitrariness of the phase position of the fourth 22 and first 19 frequency dividers, since the clock frequency f of the fourth frequency divider 22 sets the fourth pulse counter 29 to the initial position.

In the decoder 25, the first and last strobe pulses are determined with the condition that the extreme positions of these strobe pulses may not correspond to the actual position of the extreme phase strobe pulses of the parallel channels in one step of the transformed signal. Triggers 14 and 15 fix the temporal positions of the extreme phase strobe pulses, and on elements 39 and 44 the interval between the phase of the extreme strobe pulses and the phase f of the frequency Kf. Is filled in. On the second modulator 24 the selection of the pulse filled K f is made two. the time interval between the extreme in phase strobes,

The calculation of the average phase value of this time interval is carried out on the reversible counter 30 by reading from it the recorded burst of pulses at twice the frequency 2Kf to the next half-cycle frequency f in phase.

what provides-mc. c using delay element 48

per poltakt f, trigger 16, element I 40 and frequency divider 5 by two, the impulse of the middle phase pulse is conducted using the first modulator 23 modulo two and delay element 47 per frequency cycle

The implanted average pulse for one phase cycle arrives at the second input of phase discriminator 52, and at the first input the phase of frequency f. Through the block 51 add-read about eodits adjustment phase dividers 19 and 22 frequencies up until the phase f from the output of the splitter 22 frequency

does not coincide with the phase average per clock value obtained at the output of the first adder 23 modulo two.

Correct determination of the limits of the clock interval is carried out taking into account the second criterion for determining the phase position f - the criterion for grouping parallel signals,

arriving at the inputs of the device, using the delay element 49 and the trigger 19, a time interval is formed in which the grouping of strobe pulses is analyzed. The pulse of the grouping zone in the inverted form from trigger 18 and the strobe pulses of all regenerators after quantization on multiplexer 8 are tapped onto the And 43 element. If all the strobe pulses in the cycle f are in the grouping zone, then the And 43 output does not have pulses. If one or several channels leave the grouping zone, then at the output of the element

And 43 pulses appear, the number of KOTopbfx is then integrated on the pulse counter 28, and AND 41 and 42 arrive through the OR 32 element. Depending on the phase position of the phase discriminator 52 repeated by the trigger 17, the addition-subtraction block 51 is adjusted to the optimum position of phase f. However, when operating a multi-span line under special conditions, when it is necessary to transmit information in the shortest possible time for uncorrected irregularities, and group time for slowing down the parallel channels, Use the results of preliminary testing of a multi-span radio link. Such testing provides, with a certain guarantee, transmission of information with a given quality and use of test results to determine the correct f-p phase even in the case of such line signal distortions, when the channelization criteria can be fulfilled, but parallel-serial signal conversion is incorrect. When parallel-serial conversion of some test signals of type 1/1 + n (for example,

when the signal is 1/1 + n (it is the recommended 1: 7 signal recommended by CCCTT), the signal structure in the parallel channels and after the parallel-sequential

For example, when the manipulation speed in the water channels 200 after a parallel-serial conversion at a speed of 1200 water, there is also a 1: 7 signal. Therefore, sending a test signal of 1: 7 at a speed of 1200 Water under special conditions, on all sections of a multi-span line in parallel channels, is at a 1: 7 signal. at a speed of 200 Water and after a parallel-serial conversion at a speed of 1200 Water, a 1: 7 signal also acts. If the channelization is wrong, then at the output of the analyzer 3 errors of the serial test signal, error pulses are detected. In this case, the frequency f reduced by the frequency divider 20 times sh (the number w is determined by the integration time in order to eliminate the false influence of the VIA on the regenerator synchronization) is transmitted through delay element 43 (for the duration of the pulse) to the R input of the trigger 12 and the first input of the element is 37. If there are no errors from the parallel analyzer signal output from the analyzers 2j- 2t, then the pulses do not arrive at the S-input of the trigger 12 via the element OR 31. In this case, the element And 37 is open and at its output there appear pulses affecting the R input of trigger 13. If there are no error pulses from the analyzer 3 error sequential test signal, then trigger 13 opens element 38 and through element 45 delays equal to the cycle f, frequency pulses f. : m on. They start through the element 38 and arrive at the counter 27 pulses. The capacity of the pulse counter 27 determines the time of the test analysis and, if the counter, 27 pulses are filled, its output pulse sets the trigger 10 to one state. The trigger 10 locks the elements And 33-35 and blocks all the work of finding the optimal phase. Before the analysis, the radio lines on the test signal trigger 10 are unblocked by the push-button switch 6. If from the analyzer output of 3 errors of the sequential test signal there are error pulses, then the trigger 13 locks the AND 38 element, the trigger 10 opens the AND 33-35 and pulses from the output of element 45

the delay through the element 35 is fed to the counter 26 pulses. If on the error analyzers of the parallel test signal there are error-pulses, then the output of the AND 37 element does not generate pulses and the parallel channel arrangement analysis circuit for the test does not work. In the absence of errors from the output of error analyzers of parallel test signals (and parallel channels on the pulse counter 26, pulses appear arriving at the R input of the trigger 11, which opens And 36, and pulses from the output of the pulse counter 26 through delay element 50 ( for the pulse duration) go through the AND 36 element, the OR 32 element to the AND 41 or 42 elements and then to the + or - inputs of the add-subtract block 51, which changes the phase position f and in accordance with this the arrangement of the parallel channels.

Claims (1)

Invention Formula Two-stage parallel-sequential regenerator containing n-one-stage regenerators, shift register, pulse generator, first trigger, first frequency divider, addition-subtraction unit, first, second and third And elements and sequentially connected third And element, first counter pulses, the Bj-th trigger and the fourth element And the information inputs of the single-stage regenerators are information inputs of the device, the information outputs are connected to the corresponding register information inputs Shift trap, the output of which is the output | Device house, the output of the first element AND through the series-connected addition and subtraction unit and the first frequency divider is connected to another: the secondary input, the shift register and the second element I is connected to another input of the additional and subtraction unit, the output of the second trigger is connected to the first input of the first element I, characterized in that, in order to increase the accuracy of the signal regeneration, n-error analyzers of the parallel test signal are entered into it. la, third, fourth, fifth, sixth, seventh,, eighth and ninth triggers. 7 first, second, third, fourth, fifth and sixth delay elements, second, third and fourth frequency dividers, frequency divider by two, phase discriminator, reversible counter, first and second modulo two, multiplexer, p-phase distributor pulses, decoder, second, third and fourth pulse counters, first and second elements OR, fifth, sixth, seventh eighth, nine, tenth, eleventh and twelfth elements AND, a pushbutton switch, with the information outputs of one-stage regenerators via co The corresponding parallel text error analyzers are connected to the corresponding inputs of the first OR element, the output of which is connected through the third trigger, the fifth And element, the fourth trigger, the sixth And element, the second pulse counter is connected to the first input of the first trigger, the output of which is connected to the first inputs of the second and the third elements And, and the second input through the closing button. The switch is connected to the output of the fourth frequency divider, with the first inputs of the fifth, sixth, seventh and ninth trigger c, with the setup input of the fourth pulse counter, with the first input of the phase discriminator, with the input of the second frequency divider, with the clock input of the shift register, and through the fourth delay element - with the second input of the seventh trigger, whose output is through a series-connected eighth element And, a reversible counter , the third is a delay element and the first modulo-two adder is connected to the second input of the phase discriminator, the output of the reversible counter is connected to another input of the first modulo-two adder, the strobe outputs The single-stage regenerator pulses are connected to the corresponding first inputs of the multiplexer, the second inputs of which are connected to the corresponding outputs of the p-phase pulse distributor, whose input is connected to the frequency divider by two, to the clock inputs of the single-stage regenerators, to the first inputs of the seventh and twelfth elements I and through third divider, frequencies with an additional block input ten 15 20 25 246394 .8 addition and subtraction, the output of the multiplexer is connected to the first input of the eleventh element I and the information input of the fourth counter, whose information outputs are connected to the corresponding inputs of the decoder, the first output of which is connected to the second input of the sixth trigger, the output of which is connected to the second input of the seventh element And, the output of which through the second modulo two adder is connected to another input of the reversible counter, the other input of the second modulo two adder is connected to the output of the twelfth element And, the second input of which is connected to the output of the first flip-flop, the second input of which is connected to the second output of the decoder, the output of the ninth flip-flop through the serial. connected eleventh element HV, the third pulse counter, the second element OR, and the nine element AND are connected to the second input of the first element AND, the second input of the second element AND through the successively connected ten element AND and the eighth trigger are connected to the first The phase discriminator, the second output of which is connected to another input of the eighth trigger, the other output of which is connected to another input of the ninth element AND, and the second element OR is connected to another input of the tenth element And, o The first pulse counter through the sixth delay element is connected to the second input of the fourth element AND, the output of which is connected to another input of the second OR element, the output of the fourth frequency divider through the fifth delay element is connected to the second input of the ninth trigger, the output of the sixth And element is connected to another the input of the second trigger, the output of the fifth element And through the first delay element connected to another input of the sixth element And the second input of the third element And, the output of the pulse generator is connected to the divider h simplicity by two and another input of the eighth AND gate, the output device through a serial text error analyzer connected to another input of the fourth flip-flop, the output of the second frequency divider sub. keys to another input of the first element And through the second delay element to another input of the third trigger. thirty 35 40 45 50 55