SU1690209A1 - Cycle synchronization device - Google Patents

Abstract

This invention relates to multichannel telecommunications. The purpose of the invention is to improve noise immunity. A cycle synchronization device contains a sync pattern identifier 1 consisting of a shift register 2 and a decoder 3, a clock distortion analyzer 4 consisting of decoders 5 and 6 and AND 7, a switch 8 of operation mode consisting of trigger 9, And elements 10 and 11, the element He 12 and the element OR 13, the hold circuit 14, the synchronism, which includes the AND element 15, the AND-NOT element 16, the OR element 17 and the drive 18 at the output of the synchronism, the synchronism search circuit 19, consisting of elements AND 20 and 21, element OR 22, element AND-NOT 23, trigger 24 and accumulator 25 at the entrance to synchronism, as well as element I-NE 26, distortion analyzer 27, element 28, divider 29, generator node 30, clock frequency selector 31 and channel distributor 32. Protection against a false fault and false synchronization analyzer 27. The device simultaneously analyzes both sync groups and coordination control commands. Only on the basis of a generalized signal from the output of the analyzer 27 is a decision made to transfer to one or another system operation mode. 1 il. THX

Description

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The invention relates to multichannel telecommunications and can be used in digital high order transmission systems with asynchronous grouping of digital signals.

The aim of the invention is to improve noise immunity.

The drawing shows the structural electrical circuit of the device for cycle synchronization.

The cycle synchronization device contains a sync group identifier 1 consisting of a shift register 2 and a decoder 3, a clock distortion analyzer 4 consisting of decoders 5 and b and element 7, switch 8 of operation mode consisting of trigger 9, elements AND 10 and 11, the element NOT 12 and the element OR 13, the hold-up circuit 14, which includes the element AND 15, the AND-NO element 16, the OR element 17 and the drive 18 at the output of the synchronism, the synchronism search circuit 19, includes elements AND 20 and 21, element OR 22, element AND-NOT 23, trigger 24 and n storage ring 25 on entry into synchronism, and AND gate 26, E-H, distortion analyzer 27, AND gate 28, a divider 29, a generator unit 30, extractor 31, the clock 32, and a channel allocator.

The cycle synchronization device operates as follows.

The group signal is supplied to the sync signal identifier 1, which contains a shift register 2 and a decoder 3, a clock distortion analyzer, decoders 5 and b which correct the distortion in the sync group. Decoders 5 and 6 function in synchronism control mode, decoder 3 - in search mode.

The inputs of the distortion analyzer 27 receive signals that determine the correct (zero) or incorrect (one) reception of sync group control commands. In the case of three or more, out of five correctly received signals, a unit is formed at the output of the distortion analyzer 27, otherwise it is zero.

In synchronization mode, the accumulator 14 is full on the input to synchronism, the signal from its output holds trigger 9 in the closed state. As a result, the decoder circuit 3 is turned off, and the decoders 5 and 6 are in operation.

In this mode, when the trigger 9 is closed and the AND 11 element is open, when digital errors occur, the decoders 5 and 6 and the And 7 element do not react to certain types of synchro-group destruction. Allow no more than two sim distortions.

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ox sync groups If there is more than two symbol distortions in a sync group, there is no signal at one of the element 6’s gatherings, the output of element 11 and, respectively, at the output of element OR 13, the signal is also absent, since in control mode the element 10 is closed.

With two or less distortions of the symbols in the sync group, at the output of the AND 7 0 element, a signal is generated that passes through the open element AND 11, the OR element 13 and enters the input of the synchronization circuit 14, where it is compared with the signal from the generator node 30 and through the element -NOT 5 26 arrives at the first input of the analyzer 27 distortion. In the synchronism mode, at the output of the distortion analyzer 27, a signal is generated that coincides with the frequency of the cycles of the generator node 30. As a result, the accumulator 18 is out of sync output and the accumulator 25 at the synchronization input is full.

When cyclic synchronization fails (true malfunction or sync pattern distortion), accumulator 18 fills and generates an enable signal to element I 28. Pr and true cyclic synchronization failures, accumulator 25 on synchronization input is filled with synchrograms with a frequency followed by frequency divider 29 that matches with a signal from the output of the accumulator 25 generates a signal at the output of the element And 28, which establishes a new state of the generator node 30 and resets through the element OR 17 the accumulator 14 upon exit from synchronism to the zero position bottom. In the event that the out-of-sync drive 14 is filled as a result of the synchro-group distortion, then at the first undistorted sync-group, a unit appears at the output of the AND 15 element, which through the OR 17 element resets the accumulator 18 to the zero state.

Filling the accumulator 25 according to the synchronization input occurs in the case of OeX -frequent formations of code combinations identical to the synchrogram structure following the frequency divider frequency 29, In synchronism mode, the drive 25 is full and the frequency divider frequency 29 coincides with the frequency of the generator node 30. V If there is no signal from the analyzer 27 at the analyzed positions, the signal that opens the trigger 24 is generated at the output of the NE-HI element 23, and it, in turn, is the AND element 21. Next, the first codeword formed in the cycle and, identical to the synchro group, it forms a signal at the output of the E 21 and Element, which is ez0

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The trigger triggered 24 hours of use. The frequency divider 29 frequencies in the newer to the bottom. In the result, the entire search chain starts the robot with a control of the pulse sequence from the frequency divider 29, but in a different state than the previous one. At the same time, the signal from the output of the element IS-NOT 23 opens the trigger 9 and resets the drive 25 to the zero position. Its filling starts with a frequency determined by the new state of the frequency divider 29.

With simultaneous filling of accumulators 18 and 25, the first impulse from frequency divider 29 resets through element 15 and 28 the generator node 30 to a new state. The drive 21 at the input E synchronism remains filled (the control mode in the search circuit), and the drive 18 at the time of synchronization is zeroed. If the drive 18 overflowed from synchronism overflowed in the process, and the storage 25 on synchronization input has not yet been filled (and vice versa), the generator node 30 will not reset due to the absence of one 25 of the signals at the input of the E28 element.

In the case of a true synchronization failure at the output of the distortion analyzer 27, the signal does not coincide with the pulse sequence from the generator node 30. As a result, 30 a signal is generated at the output of the NAND element 23, which opens trigger 9, thereby blocking the operation of the decoders 5 and 6 and including decoder 3. At the same time, the signal from the output of the element IS-HE 23 35 opens the trigger 24. As a result, the first combination, identical to the sync group, forms a signal at the output of the decoder 3, which through the open element AND 10, the element OR 13 and the open element And 21 reset 40 sifter 29 frequency divider to a new position. If later the signals from the output of the distortion analyzer 27 coincide with the sequence from the frequency divider 29, then the accumulator 25 is filled to the synchronization input and closes trigger 3 with a signal from its output, thereby turning off the decoder 3 from operation and putting the decoders into operation 5 and 6. Otherwise, the search process is repeated .50

Thus, the trigger 9 of the operating mode switch 8 controls the operation of the decoders 3, 5 and 6. It should be noted that this device is operable both with the operation of the decoder 3 (output 55 of the trigger 9 is a constant unit) and with the operation of the decoders only 5 and 6 (at the output of the trigger 9 constant zero). When a signal arrives at the second input of trigger 9 from accumulator 25, which corresponds to its filling

The manna state (control mode in the search circuit), at the output of the trigger 9 is no signal. As a result, the element 11 is open, and the element 10 is written down — decoders are in operation.

The false analyzer 27 protects against a false layer and false synchronism. The device simultaneously analyzes the synchrogroup, trigger, and coordination control commands. Only by a generalized signal from the output of the distortion analyzer 27 is a decision made to transfer the system to a particular mode of operation.

Both in the search mode and in the synchronism mode the signal from the output of the element OR 13 is fed to the input of the element NAND 26. If this signal coincides with the sequence of pulses of the frequency divider 29, then the signal does not come to the first input of the analyzer 27 distortion. This corresponds to the presence of a sync group — true or false. Otherwise, a signal is generated at the first input of the distortion analyzer, meaning that there is no sync pattern at the corresponding positions. It should be emphasized that in synchronization mode, the decoders 5 and 6 allow opto-Tr and synchro-groups with permissible distortions. The inputs of the analyzer 27 of the Kenya receive signals about the distortion of the command for tons or from the corresponding receivers of the control commands for the matching of the transmission speeds of the asynchronous interface blocks.

The signals about the distortion of speed control commands are fed to the inputs of the distortion analyzer 27. Each pair of analyzer inputs can be connected to the corresponding outputs of the receiver of the commands for the coordination of the asynchronous interface block. These outputs can serve as the outputs of the error-correcting receiver of the commands for controlling the matching of the transmission rates. So, if three consecutive + or - commands are fixed, which indicates respectively a distortion of the + or - command, then an error signal is generated at the output of the command number counter, which is fed to the corresponding input of the proposed analyzer.

Thus, if in synchronization mode there is no signal from the output of the distortion analyzer 27, which corresponds to or lack of a synchronization group with two or more matching control commands, or only the absence of three or more control commands, a signal is generated at the output of the NAND-23 element, which blocks

trigger 9, the operation of decoders 5 and 6. A decoder 3 is entered into operation. The system has switched to the search mode. The first code combination, similar to the sync group structure, forms a single signal at the output of the decoder, which through the open element AND 10, the OR element 13 and the open element 21 resets the frequency divider 29 to a new state, simultaneously closing the trigger 24. The system goes into accumulation mode on entering synchronism. In the next cycle, the reconciliation control commands and the synchronization group are analyzed again. If there is a negative outcome (the signal at the output of the distortion analyzer 27 is absent), the device again searches for a sync pattern. Otherwise, the single signal from the distortion analyzer coincides with the sequence of pulses of the frequency separator. A unit is generated at the output of the element 20, which is recorded through the element OR 22 into the accumulator 25 at the synchronization input. When the accumulator is filled, the first signal from the frequency divider 29 will reset the generator node 30 to a new state.

Claims (1)

The invention of a cycle synchronization device comprising sequentially connected shift register and sync group descrambler, synchronization hold circuit and synchronism search circuit, the outputs of which are connected to the control inputs of the synchronism hold chain and the generator node through one of the outputs inputs synchronization hold circuits, other outputs of the generator node are connected to the corresponding inputs of the channel distributor, whose signal input connected to the corresponding inputs of the shift register and the clock frequency selector, the output of which is connected to the inputs of the generator node and the frequency divider, the output of which is connected to the corresponding input element And and with the input of the synchronization search circuit, the other output of which is connected to the control input of a frequency divider, characterized in that, in order to improve the noise immunity, a clock signal distortion analyzer connected in series, an operation mode switch, the NAND element and a distortion analyzer, the shift register's signal input connected to the corresponding the input of the clock distortion analyzer, to the other inputs of which are connected, respectively, the output of the shift register and one of the outputs of the generator node, the output of the decoder is connected to another input the switch of the operating mode, the output of which is connected to the corresponding inputs of the synchronization hold chain and the synchronism search circuit, the additional outputs of which are connected to the corresponding inputs of the operating mode switch, the output of the distortion analyzer is connected to the additional input of the synchronization search circuit, and the output of the frequency divider is connected to another input of the AND element -NOT and with the control input of the distortion analyzer, the inputs of which are the inputs of the coordination control commands.