SU1213491A1 - Device for decoding convolution code - Google Patents

Abstract

The invention relates to telecommunications and can be used in digital video information transmission systems. The invention makes it possible to increase the accuracy of the search for synchronism in a time that does not exceed the length of the code constraint of the convolutional code used. The device contains a serial-to-parallel code converter, a delay unit, control signal drivers, control signal analyzers, a switching unit, and a decoder. The pilot of the control signal contains triggers and modulo two adders. The pilot signal analyzer contains the registers, the major element, the register, the decoder, the generator of the phasing sequence of pulses, the BAN element, the trigger, the counter, the AND elements and the modulo two. The commutation block contains groups of AND elements and OR elements. 1 hp f-ly. 4 il. a (l tvD SB

Description

The invention relates to telecommunications and can be used, for example, in digital video information transmission systems.

The purpose of the invention is to increase the speed and reliability of establishing the device's frame alignment state.

FIG. Figure 1 shows a block diagram of a device for decoding a convolutional code; in fig. 2 is a functional diagram of the pilot signal generator; in fig. 3 is a functional diagram of the signal analyzer; in fig. 4 - functional circuit-switching

matrix

A device for decoding a convolutional code contains (FIG. 1) a serial code converter 1 in parallel, a delay unit 2, control signal generators 3 (syndrome), control signal analyzers 4 (syndrome), switching unit 5 and a decoder 6.

Shaper 3 control signal contains (Fig. 2) triggers 7 and adders 8 modulo two.

The analyzer 4 control signal (Fig. 3) contains the registers 9, the majority element 10, the register 11, the decoder 12, the generator 13 of the phasing sequence of pulses, the element BAN 14, the trigger 15, the counter 16, the elements And 17 and 18 and the adder 19 modulo two.

Switching unit 5 contains, 1 (FIG. 4) groups of elements 20 and 21 and elements OR 22 and 23.

The delay unit 2 can be executed on the shift registers and is intended to delay the received information sequences by the time to synchronize.

Control signal analyzers 4 are designed to determine the true numbers of received sequences.

The switching unit 5 switches the input code sequences and sequences of symbols of the syndrome to the corresponding inputs of the decoder 6 according to the control signals from the analyzers 4 of the syndrome.

The decoder 6 decodes the information sequences from the delay unit 2 by the threshold method.

The device works as follows.

To the input of the converter 1 is followed by a reference. in parallel

A sequence of characters comes from the communication channel. If reception is started at a random point in time, then the maximum shift of the true sequence numbers may be

equal to four (Fig. 1). Therefore, it is necessary to simultaneously make five attempts to determine the phase position by forming various syndromes with a shift by one,

number.

Syndromes {c- (D)}, where, ..., 5, are formed in driver 3, the inputs of which receive code combinations from converter 1 co

shift numbers by one. In the former 3 (FIG. 2), the operation of multiplying these combinations by the polynomial generators is performed, followed by summation. The generated syndromes (control signals) are sent to analyzers 4, where they are recorded in five serially connected memory registers 9. The length of each register 9 is equal to the length of the phasing sequence P (D), and the total length is approximately equal to the length of the syndrome formed in a time equal to the code limit. Since the outputs of the last bits of the registers are 9

through the majority element 10 is connected to the input of register 11, then, when the syndrome sequence passes through them, register 11 will record the result of the majority processing of five repetitions of the sequence of the sequence, distorted by the characters of the sequence S (D), formed according to criterion three of the five . Wherein

this result will also shift cyclically as the C (D) sequence progresses. With full correction of errors in the phasing sequence and its phase

the position in the register 11 this position is fixed by the decoder 12. From the output of the decoder 12, the signal about the phase position is fed to the single input of the trigger 15 and the inverse input

of the BANE element 14. In this case, the trigger 15 is transferred to the single state and the signal from its end output goes through the output of the syndrome analyzer 4 to the control input of the switching unit 5 (Fig. 1), which reallocates the input code sequences accordingly, de 5 encoder 6 from the outputs of the block 2 delay. The same signal from the direct output of the trigger 15 arrives at T | The first input element 17 (Fig. 3), allowing the passage of clock pulses to the counting input of the counter 16 and to the input of the generator 13 of the phasing sequence. In this case, the counter 16, whose capacity is equal to the number of bits of the phasing sequence P (D), sends overflow pulses to the direct input of the BAN 14 element. If the phase position is set correctly, the signal at the output of the decoder 12 will be 20 with the repetition period of the phase sequence and, entering the inverse input of the BANCH 14 element, will prohibit the overflow pulse to pass to the zero 25 trigger input 15. Thus, when confirming the phase position of the decoder 12 with a frequency equal to the period following By completing the phase sequence, the trigger 15 will 30 remain in a single state. In addition, the clock pulses from the output of the And 17 element are fed to the generator 13 of the phasing sequence, providing the generator 13 35 of the phasing sequence P (c) to the first input of the adder 19 modulo two, to the second input of which C (D) comes of the last register 9. Adder 19 subtracts 40 phasing sequence from the syndrome and at its output appears the sequence symbols S (D), which through the element 18, opened by the signal from the single output of trigger 45, arrive at the input of switching unit 5, which the outputs them to decoder 6 for error correction in the information sequences.

If in the process of receiving information 50, some number of characters that are not a multiple of FIVE are inserted or dropped, the established synchronization is violated, i.e. true syndrome will now form 55 in another shaper 3 syndrome. In this case, the analyzer 4 syndrome, which caused the true syndrome until the moment of synchronization, reveals a synchronization failure for a time not exceeding N / 2, because when three or more registers of the syndrome are filled with 9 sequences that are not equal to the true value of C (o ), the sequence P (D) of the decoder 12 will not be detected. This will prevent the fact that during the arrival of the next overflow pulse from counter 16, the element BANE J4 will remain open and the trigger 15 will be moved to the zero position. In this case, the disappearance of the signal at its direct output will cause the switching unit 5 to stop issuing input information sequences to the decoder 6, close the element 18i, prohibit the passage of the circuit to the input of the switching unit 5, and close the element 17, forbidding the clock pulses the inputs of the counter 15 and the generator 13 of the phasing signal. The single signal appearing on the inverse output of the trigger 15 sets the generator 13 and the counter 16 to the initial state.

If the reason for the synchronization was the insertion of characters in the fallout, leading to a broken nodal synchronization, then no later than through NА characters from the moment of the occurrence of the failure, the true syndrome will be highlighted in one of the four analyzers of the 4 syndromes in which the absence of synchronism was previously recorded. The process of identifying the new true syndrome will occur in the same way as in the previous case, after which the switching unit 5 will redistribute the input information sequences from the outputs of the delay unit 2, according to the input numbers of the decoder 6. The information sequences come from the outputs of the delay unit 2 to the corresponding inputs groups 20. elements I 21. The second inputs of groups 20 elements I 21 are connected to the control outputs of the analyzers of 4 syndromes. In one of the analyzers of 4 true syndrome syndromes, the control signal arrives at one of the inputs of the switching unit 5, which opens the corresponding elements of I 21. When the true syndrome is recognized, one of the syndromic

the inputs of the switching unit 5 receives a sequence with the S (D) syndrome symbol, which through the OR 23 element goes to the decoder 6. When synchronization is detected, the control signal at the control input of the switching unit 5 and the S (D) syndrome symbols at its syndrome input disappear and the output of the information sequences to the inputs of the decoder 6 is terminated. Once in another analyzer A of the syndrome, corresponding to the new distribution of input sequences, the true syndrome C (D) is identified, another control input of the switching unit 5 is connected to the control signal, and another input of the unit 5 is shown in the same sequence S (D), which with the newly redistributed input sequences will be fed to the corresponding inputs of the decoder 6.

The proposed device makes it possible to carry out a search of the phase position for a time not exceeding the length of the code constraint N; used convolutional code. In addition, the invention makes it possible to synchronize high-speed convolutional codes using threshold decoding with transmission speeds H (-1) / PfRi, while the known device is applicable for a limited class of convolutional codes with a transmission speed and requires much longer in synchronicity.

Claims (2)

1. A device for decoding a convolutional code, comprising a serial to parallel converter, the input of which is the information input of the device, the outputs of the serial to parallel converter are connected to the corresponding inputs of the delay unit, and a decoder whose output is the output of the device, characterized in that , in order to increase the speed and reliability of the device, the control signal formers, the control signal analyzers and the switching unit, respectively, are entered into it trunk inputs pilot signal drivers are combined and connected to the corresponding outputs of the serial-to-parallel converter, the outputs of the control drivers the signal is connected to the first inputs of the corresponding pilot signal analyzers, the second inputs of which are combined and are the synchronization input of the device, the first Both the second outputs of the control signal analyzers and the outputs of the delay unit are connected respectively to the first, second and third inputs of the switching unit, the first and second outputs of which are connected to the corresponding information and control inputs of the decoder. 2. The device according to claim 1, about tl and - So that the pilot signal analyzer contains a register, a major element, a group of registers, a decoder, a pulse generator, AND elements, an adder, a counter, a trigger, and a BAN element, the output of each group register is connected to the input of each subsequent group register and the corresponding major signal input element, the output of the majority element is connected to the input of the register, the outputs of which are connected to the corresponding inputs of the switch 4) of the rator, the output of the decoder is connected to the input of the installation in 1 trigger and inverse the input of the BANNER element, the output of the BANNER element is connected to the installation input on the trigger, and the direct and inverse outputs of the trigger are connected respectively to the combined first inputs of the first, second element I and to the integrated installation input on the counter and the installation input to the initial state of the pulse generator, pulse generator output connected with the first input of the adder, the second input of which is connected to the output of the last register of the group of registers, the output of the adder is connected to the second. in the first element And the output of the second element And is connected to the synchronizing input of the pulse generator and the counting input of the counter, the output of the counter is connected to the direct input 712134918 the home of the BAN, the input of the primary input AND, are respectively the first register of the register group, the second second input, the first and second you-. the input of the second element I, directly by the analyzer's control signal of the trigger and the output of the first element.  H Editor N. Dankulich Compiled by M. Nikulenkov Tehred S. Migunova Proofreader E. Roshko Order 782/58. Circulation 516 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d. A / 5 Branch ShSh Patent, Uzhgorod, st. Project, 4