SU1518905A2 - Device for extracting recurrent clock signal with error detection - Google Patents

Abstract

The invention relates to automation, remote control, electrical communication. The purpose of the invention is to reduce the duration of the transient synchronization recovery process and increase the reliability of the clock signal selection. New in the device is the input of the clock error control unit 12 and the adjustable delay unit 13. The device has two modes of operation. The first mode of operation, i.e. synchronization provides the reception and verification in block 6 of the separated checks of the 2K elements of the clock signal. Repeated reception of 2K elements is carried out as many times until 2K elements are received correctly. After that, the device is put into synchronization mode. In this mode, block 12 monitors the received sync signal. When the number of errors exceeds the allowable number by block 12, the device is switched to the first mode. 1 hp f-ly, 4 ill.

Description

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I-acquisition is related to automation, telecommunications, telecommunications, and can be used for frame synchronization in data transmission systems and is additional to the basic copyright certificate No. 1 198762.

The purpose of the invention is to reduce the duration of the transition process of synchronism recovery and to increase the reliability of the selection of the clock signal.

Fig. 1 shows the structure of the electrical circuit of the device for extracting recurrent sync signal with error detection; FIG. 2 is a diagram of a mode switch; in fig. 3 is a block diagram of the divided checks (PDU); Fig, 4 is a block diagram of the error control clock signal,

A device for separating a recurrent sync signal with error detection contains a switch 1 of operation modes, a unit 2 for recurrence checking; selector 3, first and second elements AND 4 and 5, PDU 6, third element AND 7, element OR 8, fourth element AND 9, counter 10, control trigger 11, block 1 2 of synchro error control

signal and block 13 adjustable delay.

Switch 1 contains a trigger 1A, the first and second elements And 15 and 16, the element OR 17,

PDU 6 contains 2 K-bit shift register 18, the first element is AND 19, trigger 20, adders 21, -21ts modulo two, the element OR-NOT 22, and the second element And 23, Block 12 consists of an adder with respect to

module two 24, element 25 and shift register 26, trigger 27, counter 28 element 3 AND-NOT 29 and element OR 30,

A device for extracting a recurrent clock with error detection works as follows.

The accepted sequence of binary symbols through switch 1 enters block 2, which contains the shift register on K bits with pickpoints on the modulo two adder in accordance with the polynomial F (k), and through the second element 5, to the second input of which permitting the potential from the zero output of the trigger 11, in the GRP 6 to the input 2K-raer of the common shift register 18 and to the first input of the first zlemont I 19, to the second input

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which is supplied by a raer circuit (potential from the trigger on trigger 10. The first single element of the received recurrent sync syringe 1a sets trigger 20 to one, and the first potential is supplied to the first input of the second element And 23 And 23 excludes the false trigger of the PDU 6, when the 2K-bit shift register 18 contains only zeros, Accept: e the binary elements of the recurrent clock signal are written into the 2K-bit shift register 18 PDU 6, and the counter 10 by 2K counts the number of clock cycles oystva. After 2K-2K cycles in the discharge shift register 18 BRP6 recorded 2K elemeytov recurrent .sinhrosignala, IE their last K elements is recorded in the shift register at bit K block rows 2,

If 2K elements are accepted correctly, then the system of separated checks is performed, and the output of the element ORIANA 22 will have a high resolving potential. The overflow pulse from the output of the counter 10 to 2K through the open third element And 7 sets the trigger P to the unit state, prohibiting the very further passage of the elements through the second element And 5 in PDU 6 and further counting the pulses of the clock frequency by the counter 10, since the fourth element I 9 is closed at the second input. From the output of the third element I 7, an overflow pulse also goes to the control input of the switch 1 and sets the trigger 14 to one state, which disables the third input of the switch 1 from its output and However, the second input to the output of the switch I stitches, thereby closing the feedback translates the shift register to K bits of block 2 to autonomously generating a recurrent sequence, in addition, the overflow pulse from the output of counter 10 to 2K through the OR element 8 6 and sets the 2K-bit shift register 18 and trigger 20 to the zero state, thereby preparing the elements of PDU 6 for a new work cycle.

The selector 3, connected to block 2 when the selectable K-valued combination is reached, through the first element I 4, at the second input of which

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A melting sweat from a single output of the trigger 11 and the first output I 4 produces a phasing signal. The pulse from the second output of the first element AND 4 returns the device to its original position, sets trigger 11 to the zero state and confirms the zero state of the counter 10 to 2K and PDU, and also goes to the first input of switch 1, sets trigger 14 to zero state, opening the same way, hfcJM feedback and connecting the input of switch 1 to its output.

If 2K elements of the received re- 15 trigger 26 in one state. Pa

the clock signal is not accepted correctly, then at the output of PDU 6, the low potential and overflow pulse from the output of counter 10 to 2K does not pass to the input of the third element I 7, but enters PDU 6 and sets the trigger 20 and 2K-bit shift register 18 to the zero state, preparing them to receive the next clock segment of 2K elements, And so to those 25 probabilities of errors in the channel

as long as the 2K elements are not accepted correctly,

In block 12, it is monitored whether from the moment of time after the correct reception of the 2K elements in PDU 6 until the selection of the K-valued combination in the selector 3 is reached, after which the knowledge and degree of accuracy of the tracking of the syncronism is made. When the probability of the error is small and from the moment of the occurrence of the fifth error in the sync signal, which 3Q overturns the trigger 27 in a single step, until the moment of the appearance of the overflow pulse and the output of the counter 28, i.e. imgtulso, n-capacitance of the chick 28, at the output of the register. shift

Reception and verification of the received recurrent sequence in PDU 6 through 26 are not consistent with the overflow pulse,

to the above described algorithm, the generated recurrent sequence by block 2 coincides and in some way with the received clock signal.

Prior to the appearance at the output of the third element I 7 of the pulse, t, e "during the entry into synchronism, the element ZI-HE 29 is closed at the third input by a zero potential from the single output of the trigger I 1, After the correct reception of the 2K elements of the recurrent clock signal PDU 6 pulse from the overflow from the output of the counter 10 to 2K through the open third element AND 7 and the element OR 30 enters the input of the zero-state setting of the trigger 27, the overflow pulse from the output of the counting 10 The installed trigger 11 in. A single state, with its resolving potential, opens an element ZI-HE 29 from a single output, i.e. unit 12 is prepared for operation.

Roll 12 works as follows.

The inputs of the modulo two 24 are fed by the received recurrent clock sequence and generated by the recurrent sequence by the block 2. When the elements of these sequences coincide, the output of the modulo two 24 is set to a low level, and if there is a discrepancy, a high level The first mismatch and as a result, at the output of the modulo adder, at two 24, the highest level sets

trigger 26 in one state. Pa

the input of the register 26, the counter 28, and the element AND 29 is supplied allowing the sweat. And, the counter 28 begins to count the number of clock pulses arriving at the counting input. Register 26 records the number of mismatched elements compared in the modulo two 24. The capacity of register 26 to counter 28 is selected based on the life and accuracy of tracking the syncronism mode. When the probability of a fault is small and from the moment the first error appears in the sync signal, which Q triggers trigger 27 to one state until the moment when the overflow pulse appears and the output of counter 28, i.e., during time t, is the clock period , p - the capacity of the counter 28, at the output of the register. shift

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then the overflow pulse from the output of the counter 28 flows through the OR element 30 to the input of the zero setting of the trigger 27, the trigger 27 is tilted to its original state. The trigger 27, with its signal, resets the shift register 26 and the counter 28 to its original state. When T is less than the counting time of the counter 28, t, e, from the moment of the first discrepancy at the output of the modulo two 25, at the output of the shift register 26 overflow pulse overflow, meaning that the mismatch of the mismatched signal elements exceeds the permissible number (synchronization failure), the overflow pulse from the output of register 26 through the open element ZI-HE 29 is fed to the input of the zero state trigger 1, as well as to. - do the installation of the zero state 1sh of the counter W, PDU 6 and on the nepBbfrt nkhod switch 1, Trigger I 1 opkmd1.tags in

the initial state and zero potential from the single output blocks the ZI-NO 29 element and, thus, the output of the block 12, the Device goes to a new cycle of receiving and checking the received sequence of the ne 2K elements in GRP 6 according to the above described algorithm.

The capacity of shift register 26 and counter 28 can be selected in the following manner. When the probability of distortion of single elements of the received sync signal is small, for example, the error rate does not exceed one of the K elements, the storage capacitance can be chosen 2, and the counter capacitance - K, In case of loss of synchronism, the device will be fixed when two elements of K will be distorted and the device will perform a new cycle of receiving the clock signal.

Claims (1)

Invention Formula I, An apparatus for the separation of a recurrent sync signal with error detection according to avtoev, No. 1198762, which is due to the fact that, in order to reduce the duration of the transient synchronization recovery process and to increase the reliability of the sync signal allocation, clock errors, the first and second information inputs of which are connected respectively to the information input of the device and to the second input of the mode switch, the clock input of the error control of the synchronization signal connected d 0 five Q five To the combined clock inputs of the recurrence checker, the test separation unit and the first input of the fourth element I, the control inputs and the initial installation of the error error control unit are connected respectively to the forward output of the control trigger and the fourth input of the mode switch. through the delay control unit to the first input of the fourth And element, the output of the clock error control unit is connected to the combined inverse of the first And element and the first the input of the mode switch. 2, The device according to claim, 1, characterized in that the control unit, the clock signal error contains modulo two modularly connected in series, the element H, the shift register for the g bits and the ZI-NOT element, the serially connected trigger, the counter and the element OR , the second input and output of which are connected respectively to the input of the initial installation and to the zero input of the trigger, the clock input of the block is connected to the combined second input of the And element and the counting input of the counter, which is reset to zero with the same name of the shift register On the Republic of India and the Second is the entrance of the ZI-NE element, the third entrance of which is. is the control input of the error control block of the sync signal, the output and the first and second inputs of which are connected respectively to the output of the ZI-NE element and the first and second inputs of the modulo two. .2 Ltf.3