SU664304A1 - Cycle synchronization method - Google Patents

Description

(54) CYCLIC SYNCHRONIZATION METHOD

The invention relates to synthetic telephony and can be used in the transmission of telephone signals over low-speed discrete communication channels.

A known method is a cycle: synchronization for communication systems with pulse code modulation, for example for vocoder systems, based on sequential transmission over m sub strands, forming a cycle of transmitting binary signals with an n-bit code, for example, the signal — the parameters of the speech spectrum and pitch, and detecting the beginning of the transmission cycle by decoding the recognition patterns of the beginning of the cycle, transmitted during moments of speech pauses 1.

However, with the known frame synchronization method, a high probability of failures is observed and the efficiency of using the communication channel is reduced.

I The purpose of the invention is to reduce prob. failure of frame alignment failures in conditions of acoustic noise 1 and increased efficiency using a communication channel band.

For this, in the frame synchronization method for communication systems with pulse-code modulation, for example for vocoder systems based on sequential transmission of subcategories, o6pa3iTomHM transmission cycle, binary signals with a p-bit code, for example, speech spectrum parameters both the pitch and the start of the transmission cycle by decoding the code numbers of the recognition of the beginning of the cycle, transmitted at the moments of speech pauses, when transmitted in odd transmission cycles

5 inverts the characters of the higher bits of the DVOICHNB1X signals transmitted, in one of the subcycles, and in even transmission cycles, the characters of the higher bits of the binary signals transmitted

0, in other subcycles, and when receiving from a sequence of transmitted binary signals in even and odd transmission cycles, the temporary position of binary signals with

5 inverted and non-inverted symbols, which are delayed by the transmission cycle relative to each other, are compared and, according to the time of matching of the selected binary signals, they correspond to the transmission and reception cycle.

The proposed method consists in the fact that some bits of the coded signals that invert each odd cycle are used as synchro-information, and some bits of the other part of the above signals invert each even cycle, resulting in two inverted bits from the inverted and non-inverted bits. code combinations with code distance alternating through the cycle, sharply differing from the code distance of the information (speech) signal, and then, in speech pauses, for these combinations of The reception section of the CMC system is used.

FIG. Figure 1 shows the structural electrical circuit of the device for implementing the frame synchronization method for communication systems with Shulno-code modulation; on . FIG. 2 - time diagram of the device.

The device contains a multichannel analog-to-digital converter 1, a group signal output circuit 2, (binary code), a bit inversion control circuit 3, an inverter 4, a match element 5 and 6, OR elements 7, a group signal transmission line 8, a shift register 9, the receiving part, the elements of coincidence 10 and 11 of the device 12 and 13 delays, the element of coincidence 14, the register 15 of the unit shift, the elements of coincidence 16, the output circuit of the phasing signal 17 (Fig. 1).

The device works as follows (5MV:

A multichannel analog-to-digital converter 1 encodes the signal-parameters of the vocoder (10 in this example) and sees the serial binary code over circuit 2 to the inputs of the matching elements 5 and 6, which differ from one another in the presence of an inverse output. At the moments of occurrence of code, characters of the higher bits of the spectral parameters along the T circuit, pulses are issued that open the matching match element 5, in the result of which the inverse springs appear at its output: Shy: 11 GD dBv coincidence element 6 is open. CiTr aeuriia from the outputs of the elements of coincidence 5 and 6 pod1ts on the element OR 7, at the exit of which a group signal appears, consisting of six units transmitted by ya: the positions of the higher bits, 6 spectral parameters, and the chucks, x at positions other cycle (Figure 2a, where T -. cycle period). In the next cycle, the first bit of the 5th and 7th signal parameters in Fig. 2A are shifted to the inverse of the 1SH (Fig. 2a). .

Such a law of inverting the bits of different channels in black-and-white binary data transfer cycles makes the combinations resulting in a pause drastically different from the combinations arising from the transfer of talk and, therefore, eliminates the possibility of synchronous cycle synchronization during a call. The group signal from the transmitting part is transmitted via line 8 to the receiving shift register 9, after filling, with the code combinations of the first seven channels at the positions: the leading bits of these channels result in the combination 1111110, which is fed to the coincidence element 10 and causes a pulse on its output (Fig. 26). This impulse is delaying. In device 12, the delay is at the time of transmission of one cycle. B. In the next cycle, after the shift register is filled with 9 code combinations of the first seven channels, the OOOOlOi combination occurs at the positions of the higher bits of these channels, which i calls the units on seven inputs of the 8th; input element coincidence 11.0 at the same time on the th-th input of the element coincidence 11 comes a pulse from the output of the device 12 delay. At the output of the coincidence element 11, a pulse occurs (Fig. 2c), which - is delayed for the time of one cycle by the device 13 of the pulse delay.

8 moment of filling the shift register

The 9111102 code combination appears at the higher bit positions with 9 code points, causing a pulse at the output of the match element 10, which is fed to the delay device 12 and to the input of the match element 14. A pulse from the output of the device 13 arrives at the second input of the match element 14 delays. The coincidence of the two pulses at the inputs of the coincidence element 14 knocks out a pulse at its output (Fig. 2d), which is fed to the input of the coincidence element 16 at the same time phases the shift register 15 of unit Y, at the output of which periodically the impulse takes place once a cycle. Unit 15 register unit is phased so that, during subsequent cycles, the moment of occurrence of ipulse at its output would coincide with the moment of impulse output at the output of coincidence element 14. Coincidence, time of impulses that occur on coincidence element 14 and register 15 shift unit, causes a pulse on the output circuit of the signal of phase 17 phasing of coincidence element 16 (Fig. 2e). This impulse is a faye) Weth generator of the impulse grid of the receiving part

In order to make correct (phasing) decoding of the received information signals, the inversion of the same discharge is made in the receiving part of the PCM system in the same order as it was done in the transmitting part.

Claims (1)

1. Equipment for the transmission of discrete inverse MS-5. Ed. Z. A.M. and Okuneva Yu.B. M., SV, 1970, p. 121-122, JS No. til IS IP Illll .... I.IP11PI.IIlllll i IIIIHIII four - (t