SU1587656A1 - Clock synchronization signal analyzer - Google Patents

Abstract

The invention relates to a technique for transmitting discrete information via radio and telecommunications channels. The purpose of the invention is to improve the accuracy of measurement of the characteristic moments in the presence of a shift in the carrier frequency relative to the nominal frequency. The analyzer contains a Hilbert converter 1, integrators 2 and 3, a control unit 4, multipliers 5–8, averaging blocks 9 and 10, an inverter 11, adders 12–14, integrating amplifiers 15 and 16, reset keys 17 and 18, keys 19 and 20 transmissions, quadrants 21 and 22, comparison unit 23 and memory block 24 of reference number. The goal is achieved by ensuring the formation of a clock frequency signal, the phase of which is adjusted to the characteristic moments of the analyzed multi-frequency signal. 1 hp f-ly, 2 ill.

Description

The invention relates to a technique for transmitting discrete information via radio and telecommunications channels and can be used in multichannel modems for transmitting discrete information with orthogonal signals.

The aim of the invention is to improve the accuracy of measurement of the characteristic moments in the presence of a shift in the carrier frequency relative to the nominal frequency.

FIG. 1 shows a structural electrical clock analyzer circuit for clock synchronization; in fig. 2 - control unit.

Clock synchronization signal analyzer - contains a Hilbert 1 converter, integrator 2, additional integrator 3, control block k, first, second, third and fourth multipliers 5 - B, averaging block 9, additional averaging block 10, inverter 11, first, second and third adders 12 - 1, the first and second integrating amplifiers 15 and 1b, the first and second keys 17 and 18 reset, the first and second keys

19 and 20 transmissions, quad 21, additional quad 22, comparison block 23 and count number memory block 2k, the aggregator 25 c and adder 2b being part of the averaging block 9, and the integrator 27 27 c and auxiliary block 10 averaging the adder 28, and the control unit 4. contains the reference generator 29, the first, second and third dividers 30–32 frequencies, the first ring register 33, the read signal generator 3, the form of the reset key control signal generator 35, the Zb signal generator reset, the second ring register 37 block 38 initial Noah records 1

a pulse shaping unit 39, a decoder 40, an EXCLUSIVE OR element 1, an installation k2 unit, first and second switches AZ and CC.

Consider the algorithm of the clock synchronization signal analyzer. The transmitted signal in the sending interval is

m g S. (t) 5: an, sin (,) t +

ms;

(.

(one)

where a, t w is the information amplitude and phase of the signal in the subchannel;

WITH - the frequency of the subchannel;

  initial phase of the signal; Qf. - frequency shift; M is the number of subchannels. Expression (1) is equivalent to the following:

S (t) x (t) cosQj, t + x (t) t

x (t) ZL (+ (+ (r, yn 1

  Z: a costo t + C | +

m-i

(2)

50

The signal S, f- (t) at the output of the Hilbert converter is determined by the formula

) x (t) coss2ct -. - x (t) sinOjt.

(3)

When the condition of mutual orthogonality of subchannel signals on the interval T is satisfied, the group signal in the absence of a frequency shift

satisfies one of the conditions (in the transmission interval):) - TO), or S, (t) -S (t - - Tg) (the O index underlines the absence of frequency shift). We assume for definiteness that the first of the conditions is fulfilled. This means that in the sending interval

x (t) x (t - Tg); x (t) x (t - T).

Condition (k) is the basis of the signal parameter estimation algorithm. Bearing in mind the digital signal processing, we denote the Kotelnikov process counts: x; x (t;); x x .. (tS; S (t;); S ;, S, (t-,).

We suppose that in the analyzer the samples are processed t Г1 j, where n; —samples of Gaussian interference with a given dispersion, and, accordingly, s; + n ;. Assuming that two parameters of the signal are estimated: the frequency shift $ .. carrier relative to the nominal and the shift of the characteristic moment 7 (boundaries between adjacent premises), measured relative to a certain moment of the periodic clock signal generated in the analyzer, the estimation algorithm and J we write in the form

NI i + ({t)

, Q arg - ..y.shi

+ (x

i.r

- x.

) J, (5)

where K, L is the number of samples, the arrival. In formula (9) for the relative 40 shift in terms of interference, the previous designation v. Since f ((xL, / A) is continuous with respect to about, then about (L) can be determined from the condition fp (vol, 9l) 0 (the character of the extremum

respectively, respectively, for the duration of of-A - O (the nature of the extremum of the premise T and the orthogonality interval of the sequel). From (9) may-t V V .., ..; .. Dem

T x x

ABOUT ; .. but X: them

- estimates of the corresponding i.r number of parcels, over which the values of the measured and A may be considered permanent. Formula (5) means that the values of D, S p that minimize the value of the double sum are taken for | D. Since the estimates of X ,, X |, X. d-, X are random variables, then averaging is provided in formula (5); on each parcel (number i. varies from L + 1 to K) and over the course of N parcels

50

tg / CA). f; -yy-yyyy;. |)

G. (,) Y --- G-tg; hG

g, (l)

(ten)

Substituted in (9) sinod g CA) / (7). + g (and cosoi) /

/ l, c) + rfCX), we obtain the measurement algorithm 7

 A argrninfD (,. F.V

15876566

parameters. From formulas (2) and (3) it follows that

 x; s; cosQ t; - s; (6) x; S; sin9 t; + S, .. (7)

Using formulas (6) and (7), we define the Q-divide

 )

-

)five

20

i -)

 t - l

 -; -r - X ,, /

 s

+ S

-b .r

-U, r

) cos ol +

25

thirty

35

-2 {s; .S;.,

 fS; -S;., - s- s-.) sinoc, (8)

where is oi. . Denote the double sum operator in (C) by Vl

N- A + (e +)

Z .21 D,

 1- l + ke + n1,

and taking into account (8), from (5) we obtain an algorithm for simultaneous measurement of 9 and o /

L. i IQ

RS L arg (2 + f.% + OS, L -7. S, i

  K.r4; -L, r (f ...

;. 0 (G;. H, g

fi,) arg minoi (o). (9)

In formula (9), for relative shear in terms of interference, the previous designation v. Since f ((xL, / A) is continuous with respect to about, then about (L) can be determined from the condition fp (vol, 9l) 0 (the character of the extremum of- L - O (the character of the extremum of what follows). From (9)

tg / CA). f; -yy-yyyy;. |)

G. (,) Y --- G-tg; hG

g, (l)

(ten)

Substituted in (9) sinod g CA) / (7). + g (and cosoi) /

/ l, c) + rfCX), we obtain the measurement algorithm 7

 A argrninfD (,. F.V

7 arg max

: -G: -1g - 4 ..- ь -. UT

.-.- ig-g, eG ;.

The first term in the right side of (11) does not depend on 7, therefore the algorithm

(11) is equivalent to the following:

 D arg niax (D (.i, .- bf;, - ,.) T +

.u.-br, -b) Ty (12)

It is in the formula (12) that the measurement algorithm 7 is implemented in the proposed device. ,

Algorithms (11) and (12) are written in a form intended for digital processing. For analog processing

For analog processing formula

(12) is replaced by the following:

N-1 V (0

Z I (r (t) r (t -

. .ett;

-t,) -b (Orct - T,)) dtl + TN-I AUeiiVi 4Z 1 (, (t) (t -T,) -.:

 VT

L A KUiQjT

- (t) (t - T,)) dtpy. (13)

Clock Synchronization Signal Analyzer | and works as follows.

The input signal is fed to the input of the first integrator 2 and through the Hilbert 1 converter to the input of an additional integrator 3. The inputs of the keys of the record of integrators 2 and 3 connected in parallel in accordance with the key numbers are sequentially through the Kotelnikov reading intervals from the first outputs of the recording of the control unit C from the outputs of the bits of the second ring register 37, the number of bits of which is equal to the number of Kotelnikov samples located on the interval of the sending, receives recording pulses. one

The reference generator 29 in the control unit A operates at a frequency that is more than the reference one in a number of times equal to the number of samples located on the duration of the guard interval. The first frequency divider 30, the division factor of which is equal to the specified number, divides the frequency of the generator signal 29 to the nominal one. So at the entrance

five

five

0

0

five

0

five

0

five

successive advancement of register 37 receives a readout signal. The initial record 1's PO block (after switching on the device) provides parallel recording of the unit to the first register bit 37. Thus, with successive advances at the outputs of register bits 37 sequentially during the Kotelnikovsk interval, pulses will appear that lock the integrator 2 recording keys and 3. Immediately before recording the next sample, the corresponding capacitor in integrators 2 and 3 is nullified by supplying the keys of the two integrates that are also connected in parallel in accordance with the numbers. trench on the first reset unit 4 outputs narrow pulses from the control unit 39 of pulse forming. After the end of the recording, the reset keys and the entries to this capacitor are opened, transferring this cell to the storage mode. Thus, by the end of the first premise, Kotelniki samples of the direct signal were recorded in the integrator 2, and in the integrator 3 samples of the signal coupled to him according to Hilbert were recorded. After the integrators are filled, the old ones are reset and subsequent samples are recorded again at the first integrator cells, and so on. In the second reference interval, when the advance | TG unit is in the second bit of the register 37, it is overwritten by the bus connecting the outputs of the bits of the register 37 with the inputs of parallel recording of the first ring register 33, the signal from the reference frequency coming from the output of the divider 30 on the control input of the parallel register entry 33, for the first bit of this register. The number of inputs of the parallel recording of register 33 corresponds to the number of outputs of register bits 37. The input of the sequential advancement of register 33 receives a signal directly from the output of the reference generator 29, i.e. with a frequency exceeding the reference one in the number of times equal to the number of samples located on the duration of the guard interval, therefore for one reporting interval the unit recorded in the first bit will pass the corresponding number of register bits 33. During the second reference interval

a single pulse is sequentially turned on, for example, at the outputs of the first and second bits of the specified register. When operating on the third sample interval, the census of units will occur from the third bit of register 37 to the second bit of register 33. Therefore, at this time interval, the unit is sequentially scanned first on the second and then on the third output of register 33. Signals from the outputs of the bits of the register 33, the first readout outputs of the k-block are received by the read keys, which work in the same way as the write and reset keys, in parallel, in the integrators. 2 and 3. At the same time, in each integrator, a read key closes, outputting the value of the current, recorded count to the first output of each integrator, and a read key outputting the counting value, delayed on the orthogonality interval, to the second output of each integrator. Cyclic displacement of the connection of the outputs of the bits of the register 37 with the inputs of the parallel recording of the register, the register 33 ensures the delay of the reading process from the integrators 2 and 3 relative to the recording process in order to eliminate their mutual interaction. Thus, during a single counting interval, at the outputs of integrators 2 and 3, the counts of the input signal coupled by Hilbert with the input located at the same interval and the corresponding counts delayed by the orthogonality interval are successively applied. The first multiplier 5 generates a product signal — Nu, the second multiplier 6 generates a si-1 signal. The third and fourth multipliers 7 and 8 form signals.

fr, r 1 Г ,, г -ь, г respectively. The first adder 12 and the inverter 11 form the difference between the signals of the multipliers 5 and 7: f; f; -L, fi.r. and the second adder 13 is the sum of the signals of the multipliers 6 and 8: G, -, +,

1 I 7 "-U 1, 1 g, G

About the time of the beginning of the next reference interval, the signal from the first additional output of the control unit k, coming from the reset key-control signal generator 35, opens the first 17 and second 18 reset keys. In this case, the first and second integrators 15

587656 O

and 16. begin to integrate the output signals of the adders 12 and 13 in accordance with the algorithm (12). By the end of this sample interval, the signal from the second additional output of the control unit k, coming from the non-inverting output of the second reference integrator shaper 3, closes the first and second transfer keys 19 and 20, thereby integrating the results of the integration for further processing. Immediately after the output of the key, the short circuit closes, integrating amplifiers 15 and 1b clobbered, thereby preparing them for operation at a subsequent reference interval. Thus, 2Q at each sampling interval at the outputs of the transmission keys 19 and 20 are formed in accordance with the algorithm (12) averaged over the samples located on the duration of the guard interval, signals proportional to the sum of the products of the samples. Since the input signals are continuously recorded in the integrators 2 and 3 instead of the oldest samples, according to the described algorithm, calculation of the internal sum of the Vl operator from expression (11) is carried out according to the samples. The output signal of the key 19 in parallel is fed to the inputs of the averaging unit 9. The number of memory cells in each integrator 25–25 corresponds to the number of Kotelniki samples located in the interval of 1–1 times, and the number of integrators corresponds to the number of premises participating in the formation of the time averaged result. On integrators. an averaging unit 10, which is similar in 45 to the number of integrators to averaging unit 9, is in parallel received a signal from the output of transmission key 20. The recording inputs of all the integrators 27, -27 connected in parallel in accordance with the input numbers are controlled by the same signals with a duration in the sample interval D received from the first recording outputs of the control unit 4, which record the counts to the integrators 2 and 3. Thus the output signals of keys 19 and 20 can be simultaneously recorded in all rators, 27, -27, respectively

0

five

eleven

But: on the first count - on the first Cells, on the second - on the second, and so on Next throughout the whole package. The second frequency divider 31, having a division Coefficient. Equal to the number of Kotelnikov samples located on the pulse duration interval, divides the counting frequency of the input signal to the nominal clock. The third frequency divider, having a division factor equal to the number of averaged premises, divides the frequency of the input clock signal by a number of times, equal to the number of averaged premises. The first and second switches 3 and 44 ensure the connection of their stroke for the duration of the sending (successively to each of the outputs, the number of which is at each switch, respectively, the number of averaged parcels. Since the input of the switch 44 receives a signal from. Inverting output of the driver 34 , and on the input of the switch 43 - si | - from the output of the signal generator Zb signal | Nala reset of the second .integrator, which also generates the output signal from the 1 signal of the sampling frequency from the output of the divider 30, at the outputs of the switches | 43 and 44. clock pulses; spacing of control-pulse bursts arising next to the counting frequency appear, with the burst length being the same as the sending time, and the burst frequency following the number of times the number of averaged parcels is less than the clock one. the first parcel of the write signals from the first write outputs of the control unit 4, successively arriving at the inputs of the write keys of all the integrators 25 and 27, is simultaneously read from the group integrators;

Sh

15

20

.5 | - | and, since at this time the signals at the third additional readout outputs of control unit 4, coming from the second, third and subsequent outputs of switch 44, close the readout keys of the specified integrators, and the signals at the third additional reset outputs of control unit 4, coming from the second, third and subsequent outputs of the switch 43, open to ;; uchi reset the specified integrators. At the same time, in integrators 25 and 27, during the lockout time of the recording key, successively in all the cells wasp; 158765612

There is a reset in the first third of the time (the lock key is closed, the read key is closed, the reset key is closed), the second third time is written (the write key is closed, the read key is open, the reset key is open), the read is in the last third time (the write key is closed, the key readout closed, reset key open). Thus, during the same parcel, at the reference times, information is simultaneously read simultaneously from the capacitors of the same number in all integrators of both groups, and the current information is rewritten into a pair of integrators of the same number from different groups before being read. At the outputs of adders 2b and 28, combining JULK, the output signals of the integrators, 27, -27, at each counting interval, signals averaged in accordance with the algorithm (12) over the specified number of bursts are formed. These signals go through an additional quad 22 and quad 21 to an adder 14, where a signal corresponding to 30 fUnctions of the algorithm (12) is formed. The search for the argument corresponding to the maximum of this function is carried out on a cycle equal to the duration of the parcel, by a comparison unit 23 and by a memory block 24 of a reference number. The decoder 40 connected to the outputs of the bits of the divider 31 generates an output signal which, at the corresponding output of the control unit, once for the duration of the parcel, enters the installation input of the comparator unit 23, and the first result in the comparison cycle obtained at the output of the adder 14 is written in block 23 d5 comparison. The EXCLUSIVE OR circuit 41 excludes from the signal of the reference frequency received at the output of the divider 30, the pulses received at the output of the decoder 40, thereby forming a signal arriving at the corresponding output of the control unit 4 at the control input of the comparator unit 23. At the instants marked by positive pulses of the indicated signal, the comparison unit 23 compares the voltages arriving at its input with the value of the originally recorded sample. On admission to the entrance te35

40

50

55

This value, larger than the previously recorded one, the comparison unit 23 generates a pulse at the output and rewrites a larger value. In order to accomplish the task of searching for the maximum (instead of the minimum), the inputs of the comparator, which is part of the comparison unit 23, can be swapped. The counting input of the 2k memory block of the reference number of the corresponding output of the control block k receives the signal of the readout frequency from the output of the divider 30, and the input of the installation of the 2C memory block is fed to the corresponding output of the control unit k of the clock frequency received at the output of the block 42 installation. At the beginning of the comparison cycle, a unit is recorded in block 2k, the number of the reference being compared is noted at each reference interval of the comparison cycle, as well as the output signal of the comparison unit 23 inputted to the input of the memory 2k unit is fixed to the reference number if its value is greater than the previous one. According to the Advance or Lag commands issued by the memory block 2k, if at the end of the comparison cycle the maximum count number recorded in it is either greater or less than the average number in the reference counting clock, the control block k changes the phase of the clock signal generated by the divider 31. At the same time, the signals arriving at the reset and read keys of blocks 9 and 10 averaging from the second and third additional outputs of control block k, as well as the signals of setting blocks 23 and 2k, marking the beginning of the comparison cycle, will be time-shifted relative to the signals applied to the keys of recording blocks 9 and 10 from the first averaging unit outputs the recording. k control for a certain number of reference intervals. In this case, the order of recording and reading the current results in the memory cells of the second integrators relative to the order of their arrival and a corresponding shift in the beginning of the comparison cycle will occur. The lack of adjustment of the phase of the cycle of the distribution of write pulses coming from the outputs of the bits of the register 37 and controlling the sequential closure of the write keys of the block

Codes 9 and 10 of averaging provide a record of the maximum results determined on different premises in the cells of the same number of different integrators. At the same time, when the start of the recording of the current results in the averaging blocks 9 and 10 is shifted relative to the order of their arrival, the quality of the average of the parcels does not deteriorate, i.e. maximum results are always added to maximum, previous to previous, and so on. After the phase adjustment of the signal of the divider 31 is completed, the number of the maximum sample corresponds to the average number in the comparison cycle, the Advance and Delay signals in the memory block 2k are not formed, the phase adjustment of the clock signal is completed. The clock signal, the phase of which is adjusted to the characteristic moments of the analyzed multi-frequency signal, formed at the output of the divider 31, is the output signal of the analyzer.

F

formula of invention

Jq t5 20 25 ao to

Claims (2)

1. A clock synchronization signal analyzer containing an integrator, an averaging unit, a quadrator, as well as a series-connected 35 comparison unit and a memory block of the reference number, to the control inputs of which the corresponding outputs of the control unit are connected, the first outputs of which are connected to the control inputs of the integrator, the second outputs are connected to the reset and readout inputs of the averaging block, and the corresponding outputs of the memory of the reference number are connected to the inputs of the lead and lag of the control block, different In order to improve the measurement accuracy of the characteristic moments in the presence of a carrier frequency shift 0 relative to the nominal frequency, a Hilbert converter, an additional integrator, the first multiplier, the inverter, the first adder, the first integrating amplifier, the corresponding outputs of the first reset key, are connected in series, and the first transmission key connected in series the second ne45 : a multiplier, a second adder, a second | integrating amplifier, the reset inputs of which are connected to the corresponding outputs of a second reset key, a second transfer key, an additional averaging unit, an additional quad and a third adder, la also the third and fourth multipliers, while the second input (the first adder is connected to the output of the third multiplier, the first input of which is connected to the first input of the jBToporo multiplier and the first output of the integrator, the second output of which is connected to the first input of the first multiplier and the second input of the second and second transfer keys of the multiplier The keys are connected to the second auxiliary output of the control unit, the write inputs of the averaging block and the auxiliary auxiliary block are connected to the first outputs of the control block, the reset and read inputs of the averaging block and will complement averaging block ceiling elements are connected to second and third outputs of the additional control unit, averaging unit input is connected to the output of the first transmission switch and You are a xoiq averaging block via a squarer connected to the second input of the third adder, the output of which is connected to the input of the comparison unit. The remote control of the second adder is connected to the output of the fourth multiplier, the first input of JKOToporo is connected to the second input (the first multiplier and the first output of the additional integrator, the second output of which is connected to the second inputs of the third and fourth multipliers), and the input of the integrator (connected to the input of the additional Integrator through the Hilbert converter, the additional integrator control inputs are connected to the corresponding integrator inputs, and the first and iBToporo reset keys are connected to (the first additional tional output unit (control, and inputs the control lane 2. The analyzer of claim 1, 1, 2, and — for those 4to, the averaging unit and the additional averaging unit are identical and each of them contains N integrators, where N is the number of averaged premises whose outputs are connected to the corresponding inputs of the adder, The write inputs of each of the N integrators are connected to the corresponding inputs of the other N - 1 integrators and are the write inputs of the averaging unit, the inputs and additional inputs of the reset and the readings of which are the reset and read inputs of the N integrators, and the output of the adder is the output of the averaging block. . . . 39 39 I 39 2